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PCAL6416AHF Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCAL6416AHF Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 54 page PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 24 December 2012 5 of 54 NXP Semiconductors PCAL6416A Low-voltage translating 16-bit I2C-bus/SMBus I/O expander 5. Pinning information 5.1 Pinning The exposed center pad, if used, must be connected only as a secondary ground or must be left electrically open. Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24 An empty cell indicates no ball is populated at that grid point. Fig 4. Pin configuration for VFBGA24 (3 mm 3 mm) Fig 5. Ball mapping for 3 mm 3 mm VFBGA24 (transparent top view) PCAL6416APW INT VDD(P) VDD(I2C-bus) SDA RESET SCL P0_0 ADDR P0_1 P1_7 P0_2 P1_6 P0_3 P1_5 P0_4 P1_4 P0_5 P1_3 P0_6 P1_2 P0_7 P1_1 VSS P1_0 002aaf963 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aaf964 Transparent top view P1_3 P0_4 P0_5 P1_4 P0_3 P1_5 P0_2 P1_6 P0_1 P1_7 P0_0 ADDR terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 PCAL6416AHF 002aaf966 PCAL6416AEV Transparent top view D B E C A ball A1 index area 12 34 5 P0_0 RESET SDA SCL 1 234 5 P0_2 VDD(I2C-bus) VDD(P) ADDR A B P0_3 P0_4 P0_1 P1_7 P1_6 C P0_5 P1_2 P1_4 P1_5 D P0_6 VSS P1_0 P1_1 P1_3 E P0_7 002aag244 INT |
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