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PCA9555AHF Datasheet(PDF) 3 Page - NXP Semiconductors |
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PCA9555AHF Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 39 page PCA9555A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 11 September 2012 3 of 39 NXP Semiconductors PCA9555A Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up 4. Block diagram 5. Pinning information 5.1 Pinning Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9555A PCA9555A POWER-ON RESET 002aaf807 I2C-BUS/SMBus CONTROL INPUT FILTER SCL SDA VDD INPUT/ OUTPUT PORTS P0_0 VSS 8-bit write pulse read pulse P0_2 P0_1 P0_3 P0_4 P0_5 P0_6 P0_7 INPUT/ OUTPUT PORTS P1_0 8-bit write pulse read pulse P1_2 P1_1 P1_3 P1_4 P1_5 P1_6 P1_7 A1 A0 LP FILTER VDD INT A2 Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24 PCA9555APW INT VDD A1 SDA A2 SCL P0_0 A0 P0_1 P1_7 P0_2 P1_6 P0_3 P1_5 P0_4 P1_4 P0_5 P1_3 P0_6 P1_2 P0_7 P1_1 VSS P1_0 002aaf805 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aaf806 PCA9555AHF Transparent top view P1_3 P0_4 P0_5 P1_4 P0_3 P1_5 P0_2 P1_6 P0_1 P1_7 P0_0 A0 terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 |
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