CY7C2168KV18 datasheet(8/29 Pages) CYPRESS

Part #	CY7C2168KV18

Description	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Download	29 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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8 / 29 page

CY7C2168KV18, CY7C2170KV18

Document Number: 001-58923 Rev. *E

Page 8 of 29

Application Example

Figure 2 shows two DDR II+ used in an application.

Figure 2. Application Example

DQ

A

SRAM#2

LD

CQ/CQ

K

ZQ

K

ODT

R/W BWS

BUS

MASTER

(CPU or ASIC)

DQ

Addresses

LD

R/W

R = 250ohms

Source CLK

Echo Clock1/Echo Clock1

Echo Clock2/Echo Clock2

ODT

R = 250ohms

BWS

DQ

A

SRAM#1

LD

K

ZQ

CQ/CQ

K

ODT

R/W BWS

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