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PCA6408AHK Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA6408AHK Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 40 page PCA6408A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 27 September 2012 6 of 40 NXP Semiconductors PCA6408A Low-voltage, 8-bit I2C-bus and SMBus I/O expander 6. Voltage translation Table 4 shows how to set up VDD levels for the necessary voltage translation between the I2C-bus and the PCA6408A. 7. Functional description Refer to Figure 1 “Block diagram (positive logic)”. 7.1 Device address The address of the PCA6408A is shown in Figure 5. ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses. The last bit of the slave address defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation. Table 4. Voltage translation VDD(I2C-bus) (SDA and SCL of I2C master) VDD(P) (Port P) 1.8 V 1.8 V 1.8 V 2.5 V 1.8 V 3.3 V 1.8V 5V 2.5 V 1.8 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5V 5V 3.3 V 1.8 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3V 5V 5V 1.8V 5V 2.5V 5V 3.3V 5V 5V Fig 5. PCA6408A address R/W 002aaf539 0 1 0 0 0 0 AD DR fixed slave address programmable |
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