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AD7524UQ Datasheet(PDF) 2 Page - Analog Devices |
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AD7524UQ Datasheet(HTML) 2 Page - Analog Devices |
2 / 8 page REV. B –2– AD7524–SPECIFICATIONS Limit, TA = +25 C Limit, TMIN, TMAX 1 Parameter VDD = +5 V VDD = +15 V VDD = 5 V VDD = +15 V Units Test Conditions/Comments STATIC PERFORMANCE Resolution 8 8 8 8 Bits Relative Accuracy J, A, S Versions ±1/2 ±1/2 ±1/2 ±1/2 LSB max K, B, T Versions ±1/2 ±1/4 ±1/2 ±1/4 LSB max L, C, U Versions ±1/2 ±1/8 ±1/2 ±1/8 LSB max Monotonicity Guaranteed Guaranteed Guaranteed Guaranteed Gain Error 2 ±2 1/2 ±1 1/4 ±3 1/2 ±1 1/2 LSB max Average Gain TC 3 ±40 ±10 ±40 ±10 ppm/ °C Gain TC Measured from +25 °C to TMIN or from +25°C to TMAX DC Supply Rejection, 3 ∆Gain/∆V DD 0.08 0.02 0.16 0.04 % FSR/% max ∆V DD = ± 10% 0.002 0.001 0.01 0.005 % FSR/% typ Output Leakage Current IOUT1 (Pin 1) ±50 ±50 ±400 ±200 nA max DB0–DB7 = 0 V; WR, CS = 0 V; VREF = ±10 V IOUT2 (Pin 2) ±50 ±50 ±400 ±200 nA max DB0–DB7 = VDD; WR, CS = 0 V; VREF = ±10 V DYNAMIC PERFORMANCE Output Current Settling Time 3 (to 1/2 LSB) 400 250 500 350 ns max OUT1 Load = 100 Ω, C EXT = 13 pF; WR, CS = 0 V; DB0–DB7 = 0 V to VDD to 0 V. AC Feedthrough 3 at OUT1 0.25 0.25 0.5 0.5 % FSR max VREF = ±10 V, 100 kHz Sine Wave; DB0–DB7 = at OUT2 0.25 0.25 0.5 0.5 % FSR max 0 V; WR, CS = 0 V REFERENCE INPUT RIN (Pin 15 to GND) 4 5 555 k Ω min 20 20 20 20 k Ω max ANALOG OUTPUTS Output Capacitance 3 COUT1 (Pin 1) 120 120 120 120 pF max DB0–DB7 = VDD; WR, CS = 0 V COUT2 (Pin 2) 30 30 30 30 pF max COUT1 (Pin 1) 30 30 30 30 pF max DB0–DB7 = 0 V; WR, CS = 0 V COUT2 (Pin 2) 120 120 120 120 pF max DIGITAL INPUTS Input HIGH Voltage Requirement VIH +2.4 +13.5 +2.4 +13.5 V min Input LOW Voltage Requirement VIL +0.8 +1.5 +0.5 +1.5 V max Input Current IIN ±1 ±1 ±10 ±10 µA max VIN = 0 V or VDD Input Capacitance 3 DB0–DB7 5 5 5 5 pF max VIN = 0 V WR , CS 20 20 20 20 pF max VIN = 0 V SWITCHING CHARACTERISTICS Chip Select to Write Setup Time 5 See Timing Diagram tCS tWR = tCS AD7524J, K, L, A, B, C 170 100 220 130 ns min AD7524S, T, U 170 100 240 150 ns min Chip Select to Write Hold Time tCH All Grades 0 0 0 0 ns min Write Pulse Width tWR tCS ≥ tWR, tCH ≥ 0 AD7524J, K, L, A, B, C 170 100 220 130 ns min AD7524S, T, U 170 100 240 150 ns min Data Setup Time tDS AD7524J, K, L, A, B, C 135 60 170 80 ns min AD7524S, T, U 135 60 170 100 ns min Data Hold Time tDH All Grades 10 10 10 10 ns min POWER SUPPLY IDD 1 2 2 2 mA max All Digital Inputs VIL or VIH 100 100 500 500 µA max All Digital Inputs 0 V or VDD NOTES 1Temperature ranges as follows: J, K, L versions: –40 °C to +85°C A, B, C versions: –40 °C to +85°C S, T, U versions: –55 °C to +125°C 2Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = V REF. 3Guaranteed not tested. 4DAC thin-film resistor temperature coefficient is approximately –300 ppm/ °C. 5AC parameter, sample tested @ +25 °C to ensure conformance to specification. Specifications subject to change without notice. (VREF = +10 V, VOUT1 = VOUT2 = 0 V, unless otherwise noted) |
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