EVAL-AD7450CB datasheet(6/24 Pages) AD

Part #	EVAL-AD7450CB

Description	Differential Input, 1MSPS, 12-Bit ADC in 關SO-8 and S0-8

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REV. PrJ

PRELIMINARY TECHNICAL DATA

–6–

AD7450

TERMINOLOGY

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion)

at the output of the ADC. The signal is the rms amplitude

of the fundamental. Noise is the sum of all

nonfundamental signals up to half the sampling frequency

(fS/2), excluding dc. The ratio is dependent on the number

of quantization levels in the digitization process; the more

levels, the smaller the quantization noise. The theoretical

signal to (noise + distortion) ratio for an ideal N-bit con-

verter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms

sum of harmonics to the fundamental. For the AD7450, it

is defined as:

THD (dB )

= 20 log

V2

2 +V

3

2 +V

4

2 +V

5

2 +V

6

2

V1

where V1 is the rms amplitude of the fundamental and V2,

V3, V4, V5 and V6 are the rms amplitudes of the second to

the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of

the rms value of the next largest component in the ADC

output spectrum (up to fS/2 and excluding dc) to the rms

value of the fundamental. Normally, the value of this

specification is determined by the largest harmonic in the

spectrum, but for ADCs where the harmonics are buried

in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities will create

distortion products at sum and difference frequencies of

mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation

distortion terms are those for which neither m nor n are

equal to zero. For example, the second order terms in-

clude (fa + fb) and (fa – fb), while the third order terms

include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7450 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth

are used. In this case, the second order terms are usually

distanced in frequency from the original sine waves while

the third order terms are usually at a frequency close to

the input frequencies. As a result, the second and third

order terms are specified separately. The calculation of the

intermodulation distortion is as per the THD specification

where it is the ratio of the rms sum of the individual dis-

tortion products to the rms amplitude of the sum of the

fundamentals expressed in dBs.

Aperture Delay

This is the amount of time from the leading edge of the

sampling clock until the ADC actually takes the sample.

Aperture Jitter

This is the sample to sample variation in the effective

point in time at which the actual sample is taken.

Full Power Bandwidth

The full power bandwidth of an ADC is that input fre-

quency at which the amplitude of the reconstructed

fundamental is reduced by 0.1dB or 3dB for a full scale

input.

Common Mode Rejection Ratio (CMRR)

The Common Mode Rejection Ratio is defined as the

ratio of the power in the ADC output at full-scale fre-

quency, f, to the power of a 200mV p-p sine wave applied

to the Common Mode Voltage of VIN+ and VIN- of fre-

quency fs:

CMRR (dB) = 10log(Pf/Pfs)

Pf is the power at the frequncy f in the ADC output; Pfs is

the power at frequency fs in the ADC output.

Integral Nonlinearity (INL)

This is the maximum deviation from a straight line pass-

ing through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

This is the difference between the measured and the ideal 1

LSB change between any two adjacent codes in the ADC.

Zero Code Error

This is the deviation of the midscale code transition (111...111

to 000...000) from the ideal VIN+-VIN - (i.e., 0LSB).

Positive Gain Error

This is the deviation of the last code transition (011...110 to

011...111) from the ideal VIN+-VIN- (i.e., +VREF - 1LSB), after

the Zero Code Error has been adjusted out.

Negative Gain Error

This is the deviation of the first code transition (100...000 to

100...001) from the ideal VIN+-VIN - (i.e., -VREF + 1LSB), after

the Zero Code Error has been adjusted out.

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode on the

13th SCLK rising edge (see the “Serial Interface Sec-

tion”). The track/hold acquisition time is the minimum

time required for the track and hold amplifier to remain in

track mode for its output to reach and settle to within 0.5

LSB of the applied input signal.

Power Supply Rejection (PSR)

The power supply rejection ratio is defined as the ratio of

the power in the ADC output at full-scale frequency, f, to

the power of a 200mV p-p sine wave applied to the ADC

VDD supply of frequency fs.

PSRR (dB) = 10 log (Pf/Pfs)

Pf is the power at frequency f in the ADC output; Pfs is

the power at frequency fs in the ADC output.

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