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AD7397 Datasheet(PDF) 11 Page - Analog Devices |
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AD7397 Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page AD7396/AD7397 –11– REV. 0 allowing any new Input Register data updates to directly control the DAC output voltages for single-buffered applications. For doubled-buffered applications where both DAC outputs, VOUTA and VOUTB, need to be changed simultaneously to a new value, the two inputs, LDA and LDB, can be tied together and pulsed active low in a synchronous manner. RESET ( RS) PIN Forcing the asynchronous RS pin low will set the Input and DAC registers to all zeros and the DAC output voltage will be zero volts. The reset function is useful for setting the DAC outputs to zero at power-up or after a power supply interrup- tion. Test systems and motor controllers are two of many appli- cations that benefit from powering up to a known state. The external reset pulse can be generated by the microprocessor’s power-on RESET signal, from the microprocessor, or by an external resistor and capacitor. RESET has a Schmitt trigger input which results in a clean reset function when using external resistor/capacitor generated pulses. See Table I, Control-Logic Truth. POWER SHUTDOWN ( SHDN) Maximum power savings can be achieved by using the power shutdown control function. This hardware-activated feature is controlled by the active low input SHDN pin. This pin has a Schmitt trigger input which helps to desensitize it to slowly changing inputs. By placing a logic low on this pin the internal consumption of the AD7397 or AD7397 is reduced to nanoamp levels, guaranteed to 1.5 µA maximum over the operating tem- perature range. If power is present at all times on the VDD pin while in the shutdown mode, the internal DAC register will retain the last programmed data value. This data will be used when the part is returned to the normal active state by placing the DAC back to its programmed voltage setting. Shutdown recovery time measures 80 µs. In the shutdown state the DAC output amplifier exhibits an open-circuit high-resistance state. Any load connected will stabilize at its termination voltage. If the power shutdown feature is not needed then the user should tie the SHDN pin to the V DD voltage thereby disabling this function. UNIPOLAR OUTPUT OPERATION This is the basic mode of operation for the AD7396. As shown in Figure 29, the AD7396 has been designed to drive loads as low as 5 k Ω in parallel with 100 pF. The code table for this operation is shown in Table II. DAC A DAC B VREF DIGITAL VDD DGND AGND AD7396 EXT REF C 16/14 75k 75k 100pF 100pF VOUTA VOUTB 0.1 F 10 F +2.7V TO +5.5V R 0.01 F DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. Figure 29. Unipolar Output Operation Table II. Unipolar Code Table Hexadecimal Decimal Output Number Number Voltage (V) In DAC Register In DAC Register (VREF = 2.5 V) FFF 4095 2.4994 801 2049 1.2506 800 2048 1.2500 7FF 2047 1.2494 000 0 0 The circuit can be configured with an external reference plus power supply, or powered from a single dedicated regulator or reference, depending on the application performance requirements. BIPOLAR OUTPUT OPERATION Although the AD7397 has been designed for single supply op- eration, the output can easily be configured for bipolar opera- tion. A typical circuit is shown in Figure 30. This circuit uses a clean regulated +5 V supply for power, which also provides the circuit’s reference voltage. Since the AD7397 output span swings from ground to very near +5 V, it is necessary to choose an external amplifier with a common-mode input voltage range that extends to its positive supply rail. The micropower con- sumption OP196 has been designed just for this purpose and results in only 50 µA of maximum current consumption. Con- nection of the equal-value 470 k Ω resistors results in a differen- tial amplifier mode of operation with a voltage gain of two, which produces a circuit output span of ten volts, that is, –5 V to +5 V. As the AD7397 DAC is programmed from zero- code 000H to midscale 200H to full-scale 3FFH, the circuit out- put voltage VO is set at –5 V, 0 V and +5 V (–1 LSB). The output voltage VO is coded in offset binary according to Equation 3. VOUT = [(D/512)–1] × 5 (4) where D is the decimal code loaded in the AD7397 DAC regis- ter. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption includ- ing the 470 k Ω gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same resistor material, such as metal film). If better stability is required, the power supply could be substi- tuted with a precision reference voltage such as the low dropout REF195, which can easily supply the circuit’s 262 µA of current and still provide additional power for the load connected to VO. The micropower REF195 is guaranteed to source 10 mA output drive current, but consumes only 50 µA internally. If higher resolution is required, the AD7396 can be used with the addi- tion of two more bits of data inserted into the software coding, which would result in a 2.5 mV LSB step size. Table III shows examples of nominal output voltages, VO, provided by the bipo- lar operation circuit application. |
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