AD73322LYST datasheet(30/40 Pages) AD

Part #	AD73322LYST

Description	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

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REV. 0

AD73322L

–30–

TFS

DT

SCLK

DR

RFS

ADSP-218x

DSP

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

FL0

FL1

RESET

SE

Figure 34. AD73322L Connected to ADSP-218x

FSX

DT

CLKX

DR

FSR

TMS320C5x

DSP

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

XF

RESET

SE

CLKR

Figure 35. AD73322L Connected to TMS320C5x

Cascade Operation

Where it is required to configure a cascade of up to eight codecs

(four AD73322L dual codecs), it is necessary to ensure that the

timing of the SE and

RESET signals is synchronized at each

device in the cascade. A simple D type flip flop is sufficient to

sync each signal to the master clock MCLK, as in Figure 36.

1/2

74HC74

CLK

DQ

DSP CONTROL

TO SE

MCLK

SE SIGNAL SYNCHRONIZED

TO MCLK

1/2

74HC74

CLK

DQ

DSP CONTROL

TO

RESET

MCLK

RESET SIGNAL SYNCHRONIZED

TO MCLK

Figure 36. SE and

RESET Sync Circuit for Cascaded

Operation

Connection of a cascade of devices to a DSP, as shown in Fig-

ure 37, is no more complicated than connecting a single device.

Instead of connecting the SDO and SDOFS to the DSP’s Rx

port, these are now daisy-chained to the SDI and SDIFS of the

next device in the cascade. The SDO and SDOFS of the final

device in the cascade are connected to the DSP’s Rx port to

complete the cascade. SE and

RESET on all devices are fed

from the signals that were synchronized with the MCLK using

the circuit as described above. The SCLK from only one device

need be connected to the DSP’s SCLK input(s) as all devices

will be running at the same SCLK frequency and phase.

Grounding and Layout

Since the analog inputs to the AD73322L are differential, most

of the voltages in the analog modulator are common-mode volt-

ages. The excellent common-mode rejection of the part will

remove common-mode noise on these inputs. The analog and

digital supplies of the AD73322L are independent and separately

pinned out to minimize coupling between analog and digital

sections of the device. The digital filters on the encoder section

will provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital filters also remove noise from the analog inputs

provided the noise source does not saturate the analog modula-

tor. However, because the resolution of the AD73322L’s ADC

is high, and the noise levels from the AD73322L are so low,

care must be taken with regard to grounding and layout.

TFS

DT

DR

RFS

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

SCLK

DEVICE 1

MCLK

SE

RESET

AD73322L

CODEC

SDIFS

SDI

SCLK

SDO

SDOFS

DEVICE 2

MCLK

SE

RESET

74HC74

Q1

Q2

D1

D2

FL0

FL1

ADSP-218x

DSP

Figure 37. Connection of Two AD73322Ls Cascaded to

ADSP-218x

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