AD73322AST datasheet(17/43 Pages) AD

Part #	AD73322AST

Description	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

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AD73322

–17–

REV. B

MCLK

DIVIDER

MCLK

EXTERNAL

SE

RESET

SDIFS

SDI

SERIAL PORT 1

(SPORT 1)

SERIAL REGISTER 1

SCLK

DIVIDER

SCLK

CONTROL

REGISTER

1B

CONTROL

REGISTER

1C

CONTROL

REGISTER

1D

CONTROL

REGISTER

1E

CONTROL

REGISTER

1A

CONTROL

REGISTER

1G

CONTROL

REGISTER

1F

CONTROL

REGISTER

1H

3

8

16

8

2

DMCLK INTERNAL

MCLK

DIVIDER

MCLK

EXTERNAL

SE

RESET

SDIFS2

SDI2

SERIAL PORT 2

(SPORT 2)

SERIAL REGISTER 2

SCLK

DIVIDER

CONTROL

REGISTER

2B

CONTROL

REGISTER

2C

CONTROL

REGISTER

2D

CONTROL

REGISTER

2E

CONTROL

REGISTER

2A

CONTROL

REGISTER

2G

CONTROL

REGISTER

2F

CONTROL

REGISTER

2H

3

8

16

8

2

DMCLK INTERNAL

SDOFS

SDO

SDOFS1

SDO1

Figure 14. SPORT Block Diagram

Differential Output Amplifiers

The decoder has a differential analog output pair (VOUTP and

VOUTN). The output channel can be muted by setting the

MUTE bit (CRD:7) in Control Register D. The output signal is

dc-biased to the codec’s on-chip voltage reference.

Voltage Reference

The AD73322 reference, REFCAP, is a bandgap reference that

provides a low noise, temperature-compensated reference to the

DAC and ADC. A buffered version of the reference is also made

available on the REFOUT pin and can be used to bias other

external analog circuitry. The reference has a default nominal

value of 1.2 V, but can be set to a nominal value of 2.4 V by

setting the 5VEN bit (CRC:7) of CRC. The 5 V mode is gener-

ally only usable when AVDD = 5 V.

INVERTING

OP AMPS

ANALOG

LOOP-BACK

SELECT

INVERT

SINGLE-

ENDED

ENABLE

GAIN

1

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

VREF

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

REFERENCE

AD73322

VREF

VFBN1

ANALOG GAIN

TAP

0/38dB

PGA

Figure 13. Analog Input/Output Section

The reference output (REFOUT) can be enabled for biasing

external circuitry by setting the RU bit (CRC:6) of CRC.

Analog and Digital Gain Taps

The AD73322 features analog and digital feedback paths be-

tween input and output. The amount of feedback is determined

by the gain setting which is programmed in the control registers.

This feature can typically be used for balancing the effective

impedance between input and output when used in Subscriber

Line Interface Circuit (SLIC) interfacing.

Analog Gain Tap

The analog gain tap is configured as a programmable differential

amplifier whose input is taken from the ADC’s input signal path.

The output of the analog gain tap is summed with the output of

the DAC. The gain is programmable using Control Register F

(CRF:0-4) to achieve a gain of –1 to +1 in 32 steps with muting

being achieved through a separate control setting (Control Regis-

ter F Bit 7). The gain increment per step is 0.0625. The AGT is

enabled by powering-up the AGT control bit in the power con-

trol register (CRC:1). When this bit is set (=1) CRF becomes an

AGT control register with CRF:0-4 holding the AGT coeffi-

cient, CRF:5 becomes an AGT enable and CRF:7 becomes an

AGT mute control bit. Control bit CRF:5 connects/disconnects

the AGT output to the summer block at the output of the DAC

section while control bit CRF:7 overrides the gain tap setting

with a mute, (zero gain) setting. Table VI shows the gain versus

digital setting for the AGT.

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