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AD7013 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD7013
Description  CMOS TIA IS-54 Baseband Receive Port
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7013 Datasheet(HTML) 6 Page - Analog Devices

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–6–
REV. A
AD7013
Limit at
Parameter
T
A = –40°C to +85°C
Units
Description
t
1
160
ns min
MCLK Cycle Time
t
2
65
ns min
MCLK High Time
t
3
65
ns min
MCLK Low Time
t
4
20
ns min
MCLK Rising Edge to DxCLK Rising Edge Propagation Delay
60
ns max
t
5
2t
1
ns
DxCLK Cycle Time
t
6
t
1–20
ns min
DxCLK Minimum High Time
t
7
t
1–20
ns min
DxCLK Minimum Low Time
t
8
25
ns min
DxCLK Rising Edge to FRAME IN Setup Time
t
9
10
ns min
DxCLK Rising Edge to FRAME IN Hold Time
t
10
16t
5
ns min
FRAME IN Cycle Time
t
11
25
ns min
DxCLK Rising Edge to DATA IN Setup Time
t
12
10
ns min
DxCLK Rising Edge to DATA IN Hold Time
t
13
0
ns min
FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay
25
ns max
t
14
25
ns max
MODE1 Low to FRAME OUT 3-STATE
t
15
25
ns max
MODE1 High to FRAME OUT Active
NOTE
1t
14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1.
The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
(V
AA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,
f
MCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
CONTROL SERIAL INTERFACE TIMING1
MxCLK (I)
DxCLK (O)
DATA IN (I)
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
MODE1 (I)
t
14
t
15
FRAME OUT (O)
t
13
FRAME IN (I)
t
8
t
10
DATA
DB9
DB8
DB1
DB0
A3
A0
S1
S0
ADDRESS
IGNORED
t
11
t
12
t
4
t
1
t
2
t
3
t
9
t
6
t
7
3 – STATE
t
5
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
1.6mA
IOL
CL
50pF
TO OUTPUT PIN
+2.1V
IOH
200
µA
Figure 1. Load Circuit for Digital Outputs


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