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AD568 Datasheet(PDF) 4 Page - Analog Devices |
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AD568 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 14 page  AD568 REV. A –4– their glitch impulse. It is specified as the net area of the glitch in nV-sec or pA-sec. COMPLIANCE VOLTAGE: The range of allowable voltage at the output of a current-output DAC which will not degrade the accuracy of the output current. SETTLING TIME: The time required for the output to reach and remain within a specified error band about its final value, measured from the digital input transition. TIME – ns 0.8 0 250 50 100 150 200 0.6 0.4 Figure 2. Glitch Impulse Connecting the AD568 UNBUFFERED VOLTAGE OUTPUT Unipolar Configuration Figure 3 shows the AD568 configured to provide a unipolar 0 to +1.024 V output range. In this mode, the bipolar offset termi- nal, Pin 21, should be grounded if not used for offset trimming. The nominal output impedance of the AD568 with Pin 19 grounded has been trimmed to 100 Ω, ±1%. Other output im- pedances can be generated with an external resistor, REXT, be- tween Pins 19 and 20. An REXT equalling 300 Ω will yield a total output resistance of 75 Ω, while an R EXT of 100 Ω will pro- vide 50 Ω of output resistance. Note that since the full-scale output current of the DAC remains 10.24 mA, changing the load impedance changes the unbuffered output voltage accord- ingly. Settling time and full-scale range characteristics for these load impedances are provided in the specifications table. Bipolar Configuration Figure 4 shows the connection scheme used to provide a bipolar output voltage range of 1.024 V. The bipolar offset (–0.512 V) occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc- curs when the MSB is ON with all other bits OFF (10 . . . 00), and full-scale minus 1 LSB (0.51175 V) is generated when all bits are ON (11 . . . 11). Figure 5 shows an optional bipolar mode with a 2.048 V range. The scale factor in this mode will not be as accurate as the configuration shown in Figure 4, be- cause the laser-trimmed resistor RL is not used. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT DIGITAL INPUTS 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE DIGITAL GND PLANE DIGITAL SUPPLY GROUND 100pF RTH 1k Ω +5V ANALOG OUTPUT REXT (OPTIONAL) FERRITE BEADS STACKPOLE 57-1392 OR AMIDON FB-43B-101 OR EQUIVALENT NC NC ANALOG SUPPLY GROUND Figure 3. Unipolar Output Unbuffered 0 V to +1.024 V 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15V REFCOM –15V IBPO RL ACOM LCOM SPAN SPAN THCOM VTH IOUT DIGITAL INPUTS 0.2µF 0.1µF 0.1µF 0.1µF –15V +15V ANALOG GND PLANE DIGITAL GND PLANE DIGITAL SUPPLY GROUND 100pF +5V ANALOG OUTPUT ANALOG SUPPLY GROUND Figure 4. Bipolar Output Unbuffered ±0.512 V Figure 4 also demonstrates how the internal span resistor may be used to bias the VTH pin (Pin 13) from a 5 V supply. This eliminates the requirement for an external RTH in applications that do not require the precision span resistor. BIPOLAR ZERO ERROR: The deviation of the analog output from the ideal half-scale output of 0 V (or 0 mA) for bipolar mode when only the MSB is on (100 . . .00) is called bipolar zero error. GAIN ERROR: The difference between the ideal and actual output span of FS –1 LSB, expressed in % of FS, or LSB, when all bits are on. GLITCH IMPULSE: Asymmetrical switching times in a DAC give rise to undesired output transients which are quantified by |
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