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AD5516 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD5516
Description  16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5516 Datasheet(HTML) 3 Page - Analog Devices

 
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–3–
AC CHARACTERISTICS
AD5516
(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND
= DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
1, 2
A Version
3
Unit
Conditions/Comments
Output Voltage Settling Time (Mode 1)
4
32
s max
100 pF, 5 k
Ω Load Full-Scale Change
Output Voltage Settling Time (Mode 2)
4
2.5
s max
100 pF, 5 k
Ω Load, 1 Code Increment
Slew Rate
0.85
V/ s typ
Digital-to-Analog Glitch Impulse
1
nV-s typ
1 LSB Change around Major Carry
Digital Crosstalk
5
nV-s typ
Analog Crosstalk AD5516-1
10
nV-s typ
Digital Feedthrough
1
nV-s typ
Output Noise Spectral Density @ 1 kHz
150
nV/(Hz)
1/2 typ
AD5516-1
NOTES
1See Terminology section.
2Guaranteed by design and characterization; not production tested.
3A version: Industrial temperature range –40
°C to +85°C.
4 Timed from the end of a write sequence.
Specifications subject to change without notice.
Limit at TMIN, TMAX
Parameter
1, 2, 3
(A Version)
Unit
Conditions/Comments
fUPDATE1
32
kHz max
DAC Update Rate (Mode 1)
fUPDATE2
750
kHz max
DAC Update Rate (Mode 2)
fCLKIN
20
MHz max
SCLK Frequency
t1
20
ns min
SCLK High Pulsewidth
t2
20
ns min
SCLK Low Pulsewidth
t3
15
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time
t4
5
ns min
DIN Setup Time
t5
5
ns min
DIN Hold Time
t6
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t7
10
ns min
Minimum
SYNC High Time (Standalone Mode)
t7MODE2
400
ns min
Minimum
SYNC High Time (Daisy-Chain Mode)
t8MODE1
10
ns min
BUSY Rising Edge to SYNC Falling Edge
t9MODE2
200
ns min
18th SCLK Falling Edge to
SYNC Falling Edge (Standalone Mode)
t10
10
ns min
SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
t11
4
20
ns max
SCLK Rising Edge to DOUT Valid (Daisy-Chain Mode)
t12
20
ns min
RESET Pulsewidth
NOTES
1See Timing Diagrams in Figures 1 and 2.
2Guaranteed by design and characterization; not production tested.
3All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC) and timed from a voltage level of (VIL + VIH)/2.
4This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX unless otherwise noted.)


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