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A1381 Datasheet(PDF) 7 Page - Allegro MicroSystems

Part No. A1381
Description  Programmable Linear Hall Effect Sensor ICs with Analog Output
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
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A1381 Datasheet(HTML) 7 Page - Allegro MicroSystems

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Programmable Linear Hall Effect Sensor ICs with Analog Output
Available in a Miniature Thin Profile Surface Mount Package
A1381, A1382,
A1383, and A1384
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Characteristic Definitions
Power-On Time
When the supply is ramped to its operating
voltage, the device requires a finite time to power its inter-
nal components before responding to an input magnetic field.
Power-On Time, tPO, is defined as: the time it takes for the out-
put voltage to settle within ±10% of its steady state value under
an applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
following chart.
Delay to Clamp
A large magnetic input step may cause the
clamp to overshoot its steady state value. The Delay to Clamp,
tCLP, is defined as: the time it takes for the output voltage to
settle within ±1% of its steady state value, after initially passing
through its steady state voltage, as shown in the following chart.
Quiescent Voltage Output
In the quiescent state (no significant
magnetic field: B = 0 G), the output, VOUT(Q), has a constant
ratio to the supply voltage, VCC, throughout the entire operating
ranges of VCC and ambient temperature, TA.
Guaranteed Quiescent Voltage Output Range
The quiescent
voltage output, VOUT(Q), can be programmed around its nominal
value of 2.5 V, within the guaranteed quiescent voltage range
limits: VOUT(Q)(min) and VOUT(Q)(max). The available guaran-
teed programming range for VOUT(Q) falls within the distributions
of the initial, VOUT(Q)init, and the maximum programming code
for setting VOUT(Q), as shown in the following diagram.
Average Quiescent Voltage Output Step Size
The average qui-
escent voltage output step size for a single device is determined
using the following calculation:
V
OUT(Q)maxcode –VOUT(Q)init
2n–1
Step
VOUT(Q) =
.
(1)
where:
n is the number of available programming bits in the trim
range,
2n–1 is the value of the maximum programming code in the
range, and
VOUT(Q)maxcode is the quiescent voltage output at code 2
n–1.
Quiescent Voltage Output Programming Resolution
The pro-
gramming resolution for any device is half of its programming
step size. Therefore, the typical programming resolution will be:
Err
PGVOUT(Q)(typ)
= 0.5 × StepVOUT(Q)(typ)
.
(2)
V
+t
VCC
VCC(min.)
VOUT
90% VOUT
0
t1= time at which power supply reaches
minimum specified operating voltage
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
t1
t2
tPO
VCC(typ.)
V
t
Magnetic Input
VOUT
0
t1= time at which output voltage initially
reaches steady state clamp voltage
t2= time at which output voltage settles to
within 1% of steady state clamp voltage
Note: Times apply to both high clamp
(shown) and low clamp.
VCLP(HIGH)
t1
t2
tCLP
VOUT(Q)(max)
VOUT(Q)(min)
VOUT(Q)init(typ)
Guaranteed Output
Programming
Range, VOUT(Q)
Distribution for
Max Code VOUT(Q)
Distribution for
VOUT(Q)init


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