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AD5235 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD5235
Description  Nonvolatile Memory, Dual 1024 Position Digital Potentiometers
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5235 Datasheet(HTML) 3 Page - Analog Devices

 
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PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5235
REV PrD 6 NOV, 2000
3
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (V
DD = +3V±10% to +5V±10% and VSS=0V, VA
= +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8)
Clock Cycle Time
t 1
20
ns
Input Clock Pulse Width
t 2 , t 3
Clock level high or low
10
ns
CS Setup Time
t 4
10
ns
Data Setup Time
t 5
From Positive CLK transition
5
ns
Data Hold Time
t 6
From Positive CLK transition
5
ns
CLK Shutdown Time
t 7
0
ns
CS Rise to Clock Rise Setup
t 8
10
ns
CS High Pulse Width
t 9
10
ns
CLK to SDO Propagation Delay9
t 10
RL = 1KΩ, CL < 20pF
1
25
ns
Store to Nonvolatile EEMEM Save Time10 t 11
Applies to Command 2H, 3H
25
ms
CS to SDO - SPI line acquire
t 12
ns
CS to SDO - SPI line release
t 13
ns
RDY Rise to CLK Rise
t 14
ns
Startup Time
t 15
ms
CLK Setup Time
t 16
For 1 CLK period (t4 - t3 = 1 CLK period)
ns
Preset Pulse Width
tPR
50
ns
NOTES:
1.
Typicals represent average readings at +25°C and VDD = +5V.
2.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V.
3.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
4.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
5.
Guaranteed by design and not subject to production test.
6.
PDISS is calculated from (IDD x VDD=+5V).
7.
All dynamic characteristics use VDD = +5V.
8.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are
measured using both VDD = +3V or +5V.
9.
Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
10.
Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
Timing Diagram
t
2
t
3
MS B
LS B
MS B
LS B
CL K
CS
SDI
SDO1
t
1
t
4
t
5
t
6
t
7
t
9
t
13
t
10
RD Y
t
11
t
16
MS B
LS B
SDO2
t
12
t
14
t
15
SDO 1 CLK IDLES LOW
S DO 2 CLK IDLES HIGH
t
8
Figure 1. Timing Diagram


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