Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AD5235 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD5235
Description  Nonvolatile Memory, Dual 1024 Position Digital Potentiometers
Download  10 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

AD5235 Datasheet(HTML) 5 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 5 / 10 page
background image
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5235
REV PrD 6 NOV, 2000
5
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL(408)562-7254; FAX (408)727-1550; walt.heinzer@analog.com
OPERATIONAL OVERVIEW
The AD5235 digital potentiometer is designed to operate as a true
variable resistor replacement device for analog signals that remain
within the terminal voltage range of VSS<VTERM<VDD. The basic
voltage range is limited to a VDD - VSS<5.5V. Control of the digital
potentiometer allows both scratch pad register (RDAC register)
changes to be made, as well as 100,000 times of nonvolatile
electrically erasable memory (EEMEM) register operations. The
EEMEM update process takes approximately 20.2ms, during this
time the shift register is locked preventing any changes from taking
place. The RDY pin flags the completion of this EEMEM save.
The EEMEM retention is designed to last 10 years without refresh.
The scratch pad register can be changed incrementally by using the
software controlled Increment/Decrement instruction or the Shift
Left/Right instruction command. Once an Increment, Decrement or
Shift command has been loaded into the shift register, subsequent
CS strobes will repeat this command. This is useful for push button
control applications. Alternately the scratch pad register can be
programmed with any position value using the standard SPI serial
interface mode by loading the representative data word. The
scratch pad register can be loaded with the current contents of the
nonvolatile EEMEM register under the program control. At system
power ON, the default value of the scratch pad memory is the value
previously saved in the EEMEM register. The factory EEMEM
preset value is midscale 51210.
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 24-bit instruction/address/data WORD. The write-
protect (
WP) pin provides a hardware EEMEM protection feature
disabling any changes of the present EEMEM contents.
SERIAL DATA INTERFACE
The AD5235 contains a four-wire SPI compatible digital interface
(SDI, SDO,
CS, and CLK). Key features of this interface include:
Independently Programmable Read & Write to all registers
Direct parallel refresh of all RDAC wiper registers from
corresponding EEMEM registers
Permanent storage of the present scratch pad RDAC register
values into the corresponding EEMEM register
30 bytes of user addressable electrical-erasable memory
The serial interface of AD5235 digital potentiometer uses a 24-bit
serial word loaded with MSB first. The format of the SPI
compatible word is shown in Table 1. The Command Bits (Cx)
control the operation of the digital potentiometer according to the
command instruction shown in Table 2. The Address Bits (Ax)
determine which register is activated. The Data Bits (Dx) are the
values that are loaded into the decoded register. The last
instruction executed prior to a period of no programming activity
should be the NOP instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
SE R IA L
RE G IS T E R
CO UNT E R
C O MMA ND
PR O C ES SO R
& AD D R ES S
DE CO DE
VA L ID
C O MMA ND
CS
CL K
SD I
R
PU LL U P
+5 V
SD O
GN D
PR
Figure 2. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in figure
2. The open drain output SDO is disabled whenever chip select
CS
is logic high. The SPI interface can be used in two slave modes
CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL
refer to the control bits, which dictate SPI timing in the following
microprocessors/MicroConverters: ADuC812/824, M68HC11, and
MC68HC16R1/916R1.
Table 1. AD5235 24-bit Serial Data Word
M
S
B
L
S
B
AD5235
C3
C2
C1
C0
A3
A2
A1
A0
X
X
X
X
X
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.


Html Pages

1  2  3  4  5  6  7  8  9  10 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn