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AD2S80A Datasheet(PDF) 2 Page - Analog Devices

Part No. AD2S80A
Description  Variable Resolution, Monolithic Resolver-to-Digital Converter
Download  16 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD2S80A Datasheet(HTML) 2 Page - Analog Devices

 
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AD2S80A–SPECIFICATIONS
AD2S80A
Parameter
Conditions
Min
Typ
Max
Units
SIGNAL INPUTS
Frequency
50
20,000
Hz
Voltage Level
1.8
2.0
2.2
V rms
Input Bias Current
60
150
nA
Input Impedance
1.0
M
Maximum Voltage
8V pk
REFERENCE INPUT
Frequency
50
20,000
Hz
Voltage Level
1.0
8.0
V pk
Input Bias Current
60
150
nA
Input Impedance
1.0
M
CONTROL DYNAMICS
Repeatability
1
LSB
Allowable Phase Shift
(Signals to Reference)
–10
+10
Degrees
Tracking Rate
10 Bits
1040
rps
12 Bits
260
rps
14 Bits
65
rps
16 Bits
16.25
rps
Bandwidth
1
User Selectable
ACCURACY
Angular Accuracy
A, J, S
8 +1 LSB
arc min
B, K, T
4 +1 LSB
arc min
L, U
2 +1 LSB
arc min
Monotonicity
Guaranteed Monotonic
Missing Codes (16-Bit Resolution)
A, B, J, K, S, T
4
Codes
L, U
1
Code
VELOCITY SIGNAL
Linearity
Over Full Range
±1
3
% FSD
Reversion Error
±1
±2
% FSD
DC Zero Offset2
6
mV
DC Zero Offset Tempco
–22
µV/°C
Gain Scaling Accuracy
±10
% FSD
Output Voltage
1 mA Load
±8
±9
±10.5
V
Dynamic Ripple
Mean Value
1.5
% rms O/P
Output Load
1.0
k
INPUT/OUTPUT PROTECTION
Analog Inputs
Overvoltage Protection
±8V
Analog Outputs
Short Circuit O/P Protection
±5.6
±8
±10.4
mA
DIGITAL POSITION
Resolution
10, 12, 14, and 16
Output Format
Bidirectional Natural Binary
Load
3
LSTTL
INHIBIT
3
Sense
Logic LO to Inhibit
Time to Stable Data
600
ns
ENABLE3
Logic LO Enables Position
Output. Logic HI Outputs in
ENABLE Time
High Impedance State
35
110
ns
BYTE SELECT
3
Sense
MS Byte DB1–DB8,
LS Byte DB9–DB16
LOGIC LO
LS Byte DB1–DB8,
LS Byte DB9–DB16
Time to Data Available
60
140
ns
SHORT CYCLE INPUTS
Internally Pulled High
(100 k
Ω) to +V
S
SC1
SC2
0
0
10 Bit
0
1
12 Bit
1
0
14 Bit
1
1
16 Bit
(typical at +25 C unless otherwise noted)
–2–
REV. A


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