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AD28msp01KST Datasheet(PDF) 21 Page - Analog Devices

Part No. AD28msp01KST
Description  PSTN Signal Port
Download  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD28msp01KST Datasheet(HTML) 21 Page - Analog Devices

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AD28msp01
REV. A
–21–
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high-impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time,
tMEASURED, is the interval from when a reference signal reaches a
high or low voltage level to when the output voltages have
changed by 0.5 V from the measured output high or low volt-
age. The decay time, tDECAY, is dependent on the capacitive
load, CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
t
DECAY =
C
L × 0.5 V
i
L
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start driv-
ing. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
V
+ 0.5V
OL
(MEASURED)
VOH
– 0.5V
(MEASURED)
REFERENCE
SIGNAL
OUTPUT
V
OH (MEASURED)
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS
VOLTAGE LEVEL TO BE APPROXIMATELY 1.5 V.
t
ENA
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
MEASURED
t
2.0V
1.0V
DECAY
t
OH
(MEASURED)
V
(MEASURED)
OL
V
t DIS
V
OL
(MEASURED)
Figure 18. Output Enable/Disable
Serial Ports
Parameter
Min
Max
Unit
Timing Requirement:
tSCS
SDI/SDIFS Setup before SCLK Low
10
ns
tSCH
SDI/SDIFS Hold after SCLK Low
15
ns
Switching Characteristic:
tRD
SDOFS Delay from SCLK High
30
ns
tRH
SDOFS Hold after SCLK High
0
ns
tSCDH
SDO Hold after SCLK High
0
ns
tSCDD
SDO Delay from SCLK High
30
ns
SCLK
SDIFS
SDI
MSB
2ND MSB
3RD MSB
SDOFS
SDO
t
RD
t
SCS
t
SCH
t
SCK
t
RH
t
SCDD
t
SCS
t
SCH
t
SCDH
Figure 19. Serial Ports


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