AD28MSP02KR datasheet(3/20 Pages) AD

Part No.	AD28MSP02KR

Description	Voiceband Signal Port

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Manufacturer	AD [Analog Devices]

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AD28msp02

REV. 0

–3–

D/A CONVERSION

The D/A conversion circuitry of the AD28msp02 consists of a

sigma-delta digital-to-analog converter (DAC), an analog

smoothing filter, a programmable gain amplifier, and a differen-

tial output amplifier.

DAC

The AD28msp02’s sigma-delta DAC implements digital filters

and a sigma-delta modulator with the same characteristics as the

filters and modulator of the ADC. The DAC consists of a digital

high-pass filter, an anti-imaging interpolation filter, and a digital

sigma-delta modulator.

The DAC receives 16-bit samples from the host DSP processor

via AD28msp02’s serial port at an 8 kHz rate. If the host pro-

cessor fails to write a new value to the serial port, the existing

(previous) data is read again. The data stream is filtered first by

the DAC’s high-pass filter and then by the anti-imaging interpo-

lation filter. These filters have the same characteristics as the

ADC’s anti-aliasing decimation filter and digital high-pass filter.

The output of the interpolation filter is fed to the DAC’s digital

sigma-delta modulator, which converts the 16-bit data to 1-bit

samples at a 1.0 MHz rate. The modulator noise-shapes the sig-

nal such that errors inherent to the process are minimized in the

passband of the converter. The bit stream output of the sigma-

delta modulator is fed to the AD28msp02’s analog smoothing

filter where it is converted to an analog voltage.

High-Pass Filter

The digital high-pass filter of the AD28msp02’s DAC has the

same characteristics as the high-pass filter of the ADC. The

high-pass filter removes frequency components at the low end of

the spectrum; it attenuates signal energy below the passband of

the converter. The DAC’s high-pass filter can be bypassed by

setting the DABY bit (Bit 2) of the AD28msp02’s control

register.

The high-pass filter is a 4th-order elliptic filter with a passband

cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has

the following specifications:

Filter type:

4th-order high-pass elliptic IIR

Sample frequency:

8.0 kHz

Passband cutoff:

150.0 Hz

Passband ripple:

±0.2 dB

Stopband cutoff:

100.0 Hz

Stopband ripple:

–25.00 dB

(Note that these specifications apply only to this filter, and not to the entire DAC.

The specifications can be used to perform further analysis of the exact characteris-

tics of the filter, for example using a digital filter design software package.)

Figure 3 shows the frequency response of the high-pass filter.

Interpolation Filter

The anti-imaging interpolation filter contains two stages. The

first stage is an IIR low-pass filter that interpolates the data rate

from 8 kHz to 40 kHz and removes images produced by the in-

terpolation process. The output of this stage is then interpolated

to 1.0 MHz and fed to the second stage, a sinc

4 digital filter that

attenuates images produced by the 40 kHz to 1.0 MHz inter-

polation process.

PIN DESCRIPTIONS

Pin Name

I/O/Z Function

VINNORM

I

Analog input to inverting terminal of

NORM input amplifier.

VFBNORM

O

Output terminal of NORM amplifier.

VINAUX

I

Analog input to inverting terminal of

AUX input amplifier.

VFBAUX

O

Output terminal of AUX amplifier.

VOUTP

O

Analog output from noninverting

terminal of differential output amplifier.

VOUTN

O

Analog output from inverting terminal of

differential output amplifier.

VREF

O

On-chip bandgap voltage reference

(2.5 V

± 10%).

MCLK

I

Master clock input; frequency must

equal 13.0 MHz to guarantee listed

specifications.

SCLK

O/Z

Serial clock used to clock data or control

bits to and from the serial port

(SPORT). The frequency of SCLK is

equal to the frequency of the master

clock (MCLK) divided by 5. SCLK is

3-stated when CS is low.

SDI

I

Serial data input of SPORT. Both data

and control information are input on

this pin. Input at SDI is ignored when

CS is low.

SDO

O/Z

Serial data output of SPORT. Both data

and control information are output on

this pin. SDO is 3-stated when CS is

low.

SDIFS

I

Framing signal for SDI serial transfers.

Input at SDIFS is ignored when CS is

low.

SDOFS

O/Z

Framing signal for SDO serial transfers.

SDOFS is 3-stated when CS is low.

DATA/CNTRL

I

Configures AD28msp02 for either data

or control information transfers (via

SPORT).

CS

I

Active-high chip select. Can be used to

3-state the SPORT interface; when CS

is low, the SCLK, SDO, and SDOFS

outputs are 3-stated and the SDI and

SDIFS inputs are ignored. If CS is de-

asserted during a serial data transfer, the

16-bit word being transmitted is lost.

RESET

I

Active low reset signal; resets Control

Register and clears digital filters. RESET

does not 3-state the SPORT outputs

(SCLK, SDO, SDOFS).

VCC

Analog supply voltage; nominal +5 V.

GNDA

Analog ground.

VDD

Digital supply voltage; nominal +5 V.

GNDD

Digital ground.

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