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AD28MSP02KR Datasheet(PDF) 9 Page - Analog Devices |
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AD28MSP02KR Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page AD28msp02 REV. 0 –9– Serial Output Startup Time The AD28msp02 begins transmitting data to the host processor after it is taken out of powerdown. To take the AD28msp02 out of powerdown, the host processor writes a control word to the AD28msp02. The start-up time (from the start of this control word write) before the AD28msp02 begins transmitting data is shown in Figure 11. PC Board Layout Considerations Separate analog and digital ground planes should be provided for the AD28msp02 in order to ensure the characteristics of the device’s ADC and DAC. The two ground planes should be con- nected at a single point—this is often referred to as a “Star” or “Mecca” grounding configuration. The point of connection may be at the system power supply, at the PC board power connec- tion, or at any other appropriate location. Because ground loops increase susceptibility to EMF, multiple connections between the analog and digital ground planes should be avoided. The ground planes should be designed such that all noise- sensitive areas are isolated from one another and critical signal traces (such as digital clocks and analog signals) are as short as possible. Each +5 V digital supply pin, VDD, of the AD28msp02 (SOIC Pins 20, 21) should be bypassed to ground with a 0.1 µF capaci- tor. These capacitors should be low inductance, monolithic, ce- ramic, and surface-mount. The capacitor leads and PC board traces should be as short as possible to minimize inductive ef- fects. In addition, a 10 µF capacitor should be connected be- tween VDD and ground, near the PC board power connection. MCLK Frequency The sigma-delta converters and digital filters of the AD28msp02 are specifically designed to operate at a master clock (MCLK) frequency of 13.0 MHz. MCLK must equal 13.0 MHz to guar- antee the filter characteristics and sample rate of the ADC and DAC. The AD28msp02 is not tested or characterized at any other clock frequency. A low cost crystal with a different frequency, for example 12.288 MHz, can be used for the master clock input; in this case, however, the AD28msp02 is not guaranteed to meet the specifications listed in this data sheet. SDO FIRST DATA WORD TRANSMITTED FROM AD28msp02 SCLK DATA/ CNTRL SDIFS SDOFS MSB 410 SCLK CYCLES (2050 MCLK CYCLES) SDI MSB POWERUP CONTROL WORD WRITTEN TO AD28msp02 2nd MSB 2nd MSB Figure 11. Serial Output Startup Time |
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