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AD2S100 Datasheet(PDF) 11 Page - Analog Devices |
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AD2S100 Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page AD2S100 REV. A –11– VECTOR COPROCESSOR AD2S100 ADC HOST COMPUTER ADSP-2101/ ADSP-2105 DAC AD2S80A R/D CONVERTER AD7874 DAC-8412 VECTOR COPROCESSOR AD2S100 ia, ib, ic θ INDUCTION MOTOR INV + PWM Figure 14. Advanced Motion Control Engine The magnitude of the n-th harmonic as well as the fundamental component in the power line is represented by the output of the low-pass filter, ak. In concert with magnitude of the harmonic the AD2S100 homopolar output will indicate whether the three phases are balanced or not. For more details about this application, refer to the related application note listed in the bibliography. LOW PASS FILTER e–jφ PARK TRANSFORMATION 12-BIT UP/DOWN COUNTER AD2S100 ak HOMOPOLAR OUTPUT PULSE INPUTS DIRECTION Va Vb Vc TWO-TO-THREE CLARK TRANSFORMATION Vd Vq Vd1 Vq1 Figure 15. Harmonics Measurement Using AD2S100 MULTIPLE POLE MOTORS For multi-pole motor applications where a single speed resolver is used, the AD2S100 input has to be configured to match the electrical cycle of the resolver with the phasing of the motor windings. The input to the AD2S100 is the output of a resolver- to-digital converter, e.g., AD2S80A series. The parallel output of the converter needs to be multiplied by 2 n–1, where n = the number of pole parts of the motor. In practice this is implemented by shifting the parallel output of the converter left relative to the number of pole pairs. Figure 16 shows the generic configuration of the AD2S80A with the AD2S100 for a motor with n pole pairs. The MSB of the AD2S100 is connected to MSB-(n-1) bit of the AD2S80A digi- tal output, MSB-1 bit to MSB-(n-2) bit, . . ., LSB bit to LSB bit of AD2S80A, etc. MSB MSB-1 . . . MSB – (n–1) . . . LSB + (n–1) MSB MSB-1 MSB-2 . . . . . . . LSB . . . . AD2S80A AD2S100 12,14 OR 16-BIT RESOLUTION MODE n = POLES Figure 16. A General Consideration in Connecting R/D Converter and AD2S100 for Multiple Pole Motors Figure 17 shows the AD2S80A configured for use with a four pole motor, where n = 2. Using the formula described the MSB is shifted left once AD2S80A AD2S100 BIT1 BIT2 . . . . . . BIT13 BIT14 MSB MSB-1 . . . . . . . LSB (MSB) (LSB) 14-BIT RESOLUTION MODE . . . . . . Figure 17. Connecting of R/D Converter AD2S80A and AD2S100 for Four-Pole Motor Application |
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