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AD28msp01KP Datasheet(PDF) 3 Page - Analog Devices

Part No. AD28msp01KP
Description  PSTN Signal Port
Download  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD28msp01KP Datasheet(HTML) 3 Page - Analog Devices

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AD28msp01
REV. A
–3–
PIN DESCRIPTIONS (Continued)
Name
Type Description
TCONV O
Transmit conversion clock. This clock indicates
when the ADC has finished a sampling cycle.
The frequency of TCONV is programmed by
setting the sample rate field in Control Register
0. The programmed TCONV rate can be scaled
by a factor of 8/7 by setting Bit 9 in Control
Register 1. The phase of TCONV can be
adjusted by writing the Transmit Phase Adjust
Register (Control Register 5).
RBIT
O
Receive bit rate clock. This is an output clock
whose frequency is programmable via Control
Register 2. It is synchronized with the RCONV
clock.
RBAUD O
Receive baud rate clock. This is an output clock
whose frequency is programmable via Control
Register 2. It is synchronized with the RCONV
clock.
RCONV O
Receive conversion clock. This clock indicates
when the DAC has finished a sampling cycle.
The frequency of RCONV is programmed by
setting the sample rate field in Control Register
0. The programmed RCONV rate can be scaled
by a factor of 8/7 by setting Bit 9 in Control
Register 1. The phase of RCONV can be
adjusted by writing the Receive Phase Adjust
Register (Control Register 4).
Miscellaneous
MCLK
I
AD28msp01 master clock input. The frequency
of this clock must be 13.824 MHz to guarantee
listed specifications.
RESET
I
Active-low chip reset. This signal sets all
AD28msp01 control registers to their default
values and clears the device’s digital filters.
SPORT output pins are 3-stated when RESET
is low. SPORT input pins are ignored when
RESET
is low.
CS
I
Active-high chip select. This signal 3-states all
SPORT output pins and forces the AD28msp01
to ignore all SPORT input pins. If CS is
deasserted during a serial data transfer, the
16-bit word being transmitted is lost.
Power Supplies
VCC
Analog supply voltage (nominally +5 V)
GNDA
Analog ground
VDD
Digital supply voltage (nominally +5 V)
GNDD
Digital ground
FUNCTIONAL DESCRIPTION
A/D Conversion
The A/D conversion circuitry of the AD28msp01 consists of an
analog input amplifier and a sigma-delta analog-to-digital con-
verter (ADC). The analog input signal to the AD28msp01 must
be ac coupled.
Analog Input Amplifier
The analog input amplifier is internally biased by an on-chip
voltage reference in order to allow operation of the AD28msp01
with a +5 V power supply.
Input signal level to the sigma-delta modulator should not ex-
ceed VINMAX, which is specified under “Analog Interface Electri-
cal Characteristics.” Refer to “Analog Input” in the “Design
Considerations” section of this data sheet for more information.
ADC
The ADC consists of a 3rd-order analog sigma-delta modulator,
a decimation filter, an anti-aliasing low-pass filter, and a high-
pass filter. The analog input is applied to the input amplifier.
The output of this amplifier is applied to an analog sigma-delta
modulator which noise-shapes it and produces 1-bit samples at
a 1.7280 MHz rate. This bit stream is fed to the decimation
filter, which increases the resolution to 16-bits and decreases the
sampling frequency. The parallel data stream is then processed
by the anti-aliasing low-pass filter which further reduces the
sampling rate. Finally, the high-pass filter removes input fre-
quency components at the low end of the spectrum.
Either the high-pass filter alone or the high-pass/anti-aliasing
low-pass filter combination can be bypassed by setting the
appropriate bits in Control Register 1, thus producing samples
at 7.2/8.0/9.6 kHz or 28.8/32.0/38.4 kHz, respectively. The gain
and the frequency response of the AD28msp01 are altered when
these filters are bypassed. The DSP processor that receives
samples from the AD28msp01 may need to compensate for this
change.
Decimation Filter
The decimation filter is a sinc
4 digital filter that increases resolu-
tion to 16 bits and reduces the sample rate to 28.8, 32.0, or
38.4 kHz (depending on the input sample rate). The 16 bit, par-
allel data stream output of the decimation filter is then pro-
cessed by the anti-aliasing low-pass filter.
Anti-Aliasing Low-Pass Filter
The anti-aliasing low-pass filter further reduces the sampling
rate by a factor of four to 7.2 kHz, 8.0 kHz, or 9.6 kHz (de-
pending on the output sample rate of the decimation filter). The
output is fed to the high-pass filter. The low-pass/high-pass filter
combination can be bypassed by setting the appropriate bits in
Control Register 1. If the filters are bypassed, the signal must be
scaled by the following multipliers to achieve normal levels:
2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz.
When the filters are bypassed, the host DSP must be able to re-
ceive data at the 28.8/32.0/38.4 kHz rates. In this case,
resampling interpolation should be disabled because of insuffi-
cient bandwidth to transmit both ADC and resampled data to
the SPORT.
High-Pass Filter
The digital high-pass filter removes frequency components at
the low end of the spectrum. The high pass filter can be by-
passed by setting the appropriate bits in Control Register 1.


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