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AD28MSP01 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD28MSP01
Description  PSTN Signal Port
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD28MSP01 Datasheet(HTML) 6 Page - Analog Devices

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AD28msp01
REV. A
–6–
and receive timing as well as an additional clock signal for serial
port timing.
The receive clocks are the RCONV, RBIT and RBAUD signals.
The individual clock rates are programmable and are all syn-
chronized with RCONV.
The transmit clocks are the TCONV, TBIT and TBAUD sig-
nals. The individual clock rates are programmable and are all
synchronized with TCONV.
Depending on the operating mode, the converter clocks can be
synchronized to an external clock signal (TSYNC) or can be
generated internally. The clocks can be adjusted in phase by set-
ting the appropriate phase adjust register. All the AD28msp01
Bit/Baud clocks have a 50% duty cycle except the 1600 Hz baud
rate. This baud rate has a 33%–66% duty cycle.
Resampling Interpolation Filter
The resampling interpolation filter interpolates the data from
the TCONV rate to 1.7280 MHz. The data is then resampled
(decimated) in phase with the RCONV clock. The frequency re-
sponse characteristics of the resampling interpolation filter are
identical to the frequency response characteristics of the anti-
imaging, low-pass filter/interpolation filter combination.
Figure 5 illustrates the effects of a resampling interpolation
filter.
ANALOG SIGNAL
SAMPLED AT 9600 Hz
OUTPUT OF
INTERPOLATION
FILTER
OUTPUT OF
RESAMPLING
FILTER
Figure 5. Effects of Interpolation Filter
AX0 = DM(I2, M1);
{Read data word}
AY0 = 8;
{Verify AD28msp01 address = 8}
AR = AX1 – AY0;
IF EQ JUMP goodstuff;
RTI;
goodstuff;
MODIFY (I3, M1);
{Point to second word of TX buffer}
DM(I3, M0) = AX0;
MX1 = 6;
{Load address word into MX1}
AR = 0x06a7;
{Enable TX and RX autobuffer}
DM(0x3ff3) = AR;
{Write to SPORT control Register}
TX0 = MX1;
{Autobuffer start}
RTI;
.ENDMOD;
Figure 4. AD28msp01 Initialization and ADSP-2101 Loopback Routine
Serial Data Output
When the digital power-down bit (PWDD) of Control Register 1
is set to 1, the AD28msp01’s SPORT begins transmitting data to
the host processor. All transfers between the host processor and
the AD28msp01 consist of a serial data output frame sync
(SDOFS) followed by a 16-bit address word, then a second
frame sync followed by a 16-bit data word. Address/data word
pairs are transmitted whenever they become available. The
ADC takes precedence over the Interpolator output data. If a
new word becomes available while a serial transfer is in progress,
the current serial transfer is completed before the new word starts
transmission.
Serial Data Input
The host processor must initiate data transfers to the
AD28msp01 by asserting the serial data input frame sync
(SDIFS) high. Each of the 16-bit address word and 16-bit data
word transfers begins one serial clock cycle after SDIFS is as-
serted. The address word always precedes the data word. The
second serial data input frame sync for the data word can be as-
serted as early as the last bit of the address word is transmitted,
or any time after.
The host processor must assert SDIFS shortly after the rising
edge of SCLK and must maintain SDIFS high for one cycle be-
cause SDIFS is clocked by the SCLK falling edge. Data is then
driven from the host processor shortly after the rising edge of
the next SCLK and is clocked into the AD28msp01 on the fall-
ing edge of SCLK in that cycle. Each bit of a 16-bit address and
16-bit data word is thus clocked into the AD28msp01 on the
falling edge of SCLK (MSB first).
If SDIFS is asserted high again before the end of the present
data word transfer, it is not recognized until the falling edge of
SCLK in the last (LSB) cycle.
When the serial port receives an interpolator or DAC input
word, it writes the value to an internal register which is read by
the AD28msp01 when it is needed. This allows the host to send
data words at any time during the sample period.
NOTE: Exact SPORT timing requirements are defined in the
“Specifications” section of this data sheet.
Clock Generation
The AD28msp01 generates all transmit and receive clocks
necessary to implement standard voice-grade modems. The
AD28msp01 can generate six different clock signals for transmit


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