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AD1893JST Datasheet(PDF) 6 Page - Analog Devices

Part # AD1893JST
Description  Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1893JST Datasheet(HTML) 6 Page - Analog Devices

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AD1893
–6–
REV. A
Output Control Signals
Pin Name DIP
LQFP
I/O
Description
BKPOL_O 19
25
I
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on
rising.
MODE0_O 18
24
I
Serial mode zero control for output port.
MODE1_O 17
21
I
Serial mode one control for output port.
MODE0_O
MODE1_O
0
0
Left-justified, no MSB delay, LR_O clock triggered.
0
1
Left-justified, MSB delay, LR_O clock triggered.
1
0
Right-justified, MSB delayed 16 bit clock periods from LR_O transition.
1
1
WCLK_O triggered, no MSB delay.
Miscellaneous
Pin Name DIP
LQFP
I/O
Description
XTAL_O
1
40
O
Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies
(FS word rates) from 8 kHz to 56 kHz.
XTAL_I
2
42
I
Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies
(FS word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator
with an external clock source.
RESET
13
14
I
Active LO reset. Set HI for normal chip operation.
MUTE_O
16
20
O
Mute output. HI indicates that data is not currently valid due to read and write FIFO
memory pointer overlap. LO indicates normal operation.
MUTE_I
15
18
I
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to
MUTE_O. Reset LO for normal operation.
SETLSLW 28
38
I
Settle slowly to changes in sample rates. HI: Slow-settling mode (
≈800 ms). Less sensitive
to sample clock jitter. LO: Fast-settling mode (
≈200 ms). Some narrow-band noise
modulation may result from jitter on the LR clocks. This signal may be asynchronous with
respect to the crystal frequency, and dynamically changed, but is normally pulled up or
pulled down on a static basis.
PWRDWN 27
36
I
Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal
operation.
NC
9, 20
1, 5, 8, 11,
No connect. Reserved. Do not connect.
12, 15, 17,
19, 22, 23,
26, 29, 33,
34, 37, 39,
41, 44
Power Supply Connections
Pin Name
DIP
LQFP
I/O
Description
VDD
7, 22
6, 28
I
Positive digital voltage supply.
GND
8, 14, 21
7, 16, 27
I
Digital ground. Pin 14 (DIP) and Pin 16 (LQFP) need not be decoupled.


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