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CBTL04083ABS Datasheet(PDF) 5 Page - NXP Semiconductors |
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CBTL04083ABS Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 20 page CBTL04083A_CBTL04083B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 25 June 2012 5 of 19 NXP Semiconductors CBTL04083A; CBTL04083B 3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 [1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. B0_P 38 37 I/O channel 0, port B differential signal input/output B0_N 37 36 I/O B1_P 36 33 I/O channel 1, port B differential signal input/output B1_N 35 32 I/O B2_P 29 28 I/O channel 2, port B differential signal input/output B2_N 28 27 I/O B3_P 27 24 I/O channel 3, port B differential signal input/output B3_N 26 23 I/O C0_P 34 3 I/O channel 0, port C differential signal input/output C0_N 33 4 I/O C1_P 32 7 I/O channel 1, port C differential signal input/output C1_N 31 8 I/O C2_P 25 12 I/O channel 2, port C differential signal input/output C2_N 24 13 I/O C3_P 23 16 I/O channel 3, port C differential signal input/output C3_N 22 17 I/O SEL 9 30 CMOS single-ended input operation mode select SEL = LOW: A → B SEL = HIGH: A → C XSD01 41 40 CMOS single-ended input Shutdown pin; should be driven LOW or connected to GND for normal operation. When HIGH, channel 0 and channel 1 are switched off (non-conducting high-impedance state), and supply current consumption is minimized. XSD23 19 20 CMOS single-ended input Shutdown pin; should be driven LOW or connected to GND for normal operation. When HIGH, channel 2 and channel 3 are switched off (non-conducting high-impedance state), and supply current consumption is minimized. VDD 5, 8, 13, 18, 20, 30, 40, 42 9, 19, 21, 26, 31, 34, 39, 41 power positive supply voltage, 3.3 V ± 10 % GND[1] 1, 4, 10, 14, 17, 21, 39, center pad 18, 22, 25, 29, 35, 38, 42, center pad ground supply ground Table 2. Pin description …continued Symbol Pin Type Description CBTL04083A CBTL04083B |
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