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AD5144BRUZ100 Datasheet(PDF) 10 Page - Analog Devices

Part No. AD5144BRUZ100
Description  The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5144BRUZ100 Datasheet(HTML) 10 Page - Analog Devices

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AD5124/AD5144/AD5144A
Data Sheet
Rev. A | Page 10 of 36
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Description
t1
VLOGIC > 1.8 V
20
ns
SCLK cycle time
VLOGIC = 1.8 V
30
ns
t2
VLOGIC > 1.8 V
10
ns
SCLK high time
VLOGIC = 1.8 V
15
ns
t3
VLOGIC > 1.8 V
10
ns
SCLK low time
VLOGIC = 1.8 V
15
ns
t4
10
ns
SYNC-to-SCLK falling edge setup time
t5
5
ns
Data setup time
t6
5
ns
Data hold time
t7
10
ns
SYNC rising edge to next SCLK fall ignored
t82
20
ns
Minimum SYNC high time
t93
50
ns
SCLK rising edge to SDO valid
t10
500
ns
SYNC rising edge to SDO pin disable
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Refer to t
EEPROM_PROGRAM
and tEEPROM_READBACK for memory commands operations (see Table 6).
3
RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. I2C Interface
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Description
fSCL2
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
t1
Standard mode
4.0
µs
SCL high time, tHIGH
Fast mode
0.6
µs
t2
Standard mode
4.7
µs
SCL low time, tLOW
Fast mode
1.3
µs
t3
Standard mode
250
ns
Data setup time, tSU; DAT
Fast mode
100
ns
t4
Standard mode
0
3.45
µs
Data hold time, tHD; DAT
Fast mode
0
0.9
µs
t5
Standard mode
4.7
µs
Setup time for a repeated start condition, tSU; STA
Fast mode
0.6
µs
t6
Standard mode
4
µs
Hold time (repeated) for a start condition, tHD; STA
Fast mode
0.6
µs
t7
Standard mode
4.7
µs
Bus free time between a stop and a start condition, tBUF
Fast mode
1.3
µs
t8
Standard mode
4
µs
Setup time for a stop condition, tSU; STO
Fast mode
0.6
µs
t9
Standard mode
1000
ns
Rise time of SDA signal, tRDA
Fast mode
20 + 0.1 CL
300
ns
t10
Standard mode
300
ns
Fall time of SDA signal, tFDA
Fast mode
20 + 0.1 CL
300
ns
t11
Standard mode
1000
ns
Rise time of SCL signal, tRCL
Fast mode
20 + 0.1 CL
300
ns
t11A
Standard mode
1000
ns
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 5)
Fast mode
20 + 0.1 CL
300
ns


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