Data Sheet

ADF41020

Rev. 0 | Page 15 of 16

APPLICATIONS INFORMATION

INTERFACING

The ADF41020 has a simple 1.8 V and 3 V SPI-compatible

serial interface for writing to the device. CLK, DATA, and

LE control the data transfer. When LE goes high, the 24 bits

clocked into the input register on each rising edge of CLK

are transferred to the appropriate latch. See Figure 2 for the

timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz.

ADuC7020 Interface

Figure 18 shows the interface between the ADF41020 and the

ADuC7019 to ADuC7023 family of analog microcontrollers.

The ADuC70xx family is based on an AMR7 core, although the

same interface can be used with any 8051-based micro-

controller. The microcontroller is set up for SPI master mode

with CPHA = 0. To initiate the operation, the I/O port driving

LE is brought low. Each latch of the ADF41020 needs a 24-bit

word. This is accomplished by writing three 8-bit bytes from the

microcontroller to the device. When the third byte is written,

bring the LE input high to complete the transfer.

On first applying power to the ADF41020, it needs three writes

(one each to the function latch, R counter latch, and N counter

latch) for the output to become active.

I/O port lines on the microcontroller are also used to control

power-down (CE input) and to detect lock (MUXOUT

configured as lock detect and polled by the port input).

When operating in the mode described, the maximum SPI

transfer rate of the ADuC7023 is 20 Mbps. This means that

the maximum rate at which the output frequency can be

changed is 833 kHz. If using a faster SPI clock, ensure

adherence to the SPI timing requirements listed in Table 1.

Figure 18. ADuC70xx-to-ADF41020 Interface

Blackfin BF527 Interface

Figure 19 shows the interface between the ADF41020 and

the Blackfin® ADSP-BF527 digital signal processor (DSP). The

ADF41020 needs a 24-bit serial word for each latch write. The

easiest way to accomplish this using the Blackfin family is to

use the autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for 8 bits and use three memory locations for each 24-bit

word. To program each 24-bit latch, store the three 8-bit bytes,

enable the autobuffered mode, and write to the transmit register

of the DSP. This last operation initiates the autobuffer transfer.

As in the microcontroller case, ensure the clock speeds are

within the maximum limits outlined in Table 1.

Figure 19. ADSP-BF527-to-ADF41020 Interface

PCB DESIGN GUIDELINES

The lands on the LFCSP (CP-20) are rectangular. The printed

circuit board (PCB) pad for these should be 0.1 mm longer than

the package land length and 0.05 mm wider than the package

land width. Center the land on the pad to ensure that the solder

joint size is maximized. The bottom of the LFCSP has a central

thermal pad.

The thermal pad on the PCB should be at least as large as the

exposed pad. To avoid shorting, on the PCB, provide a

clearance of at least 0.25 mm between the thermal pad and the

inner edges of the pad pattern.

Thermal vias may be used on the PCB thermal pad to improve

thermal performance of the package. If vias are used, they should

be incorporated in the thermal pad at 1.2 mm pitch grid. The

via diameter should be between 0.3 mm and 0.33 mm, and plate

the via barrel with 1 oz copper to plug the via.

Connect the PCB thermal pad to GND.

CLK

DATA

LE

CE

MUXOUT

(LOCK DETECT)

MOSI

ADF41020

SCLOCK

I/O PORTS

ADuC70xx

CLK

DATA

LE

CE

MUXOUT

(LOCK DETECT)

MOSI

ADF41020

SCK

I/O FLAGS