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AD5122A Datasheet(PDF) 13 Page - Analog Devices

Part No. AD5122A
Description  The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP.
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5122A Datasheet(HTML) 13 Page - Analog Devices

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Data Sheet
AD5122A/AD5142A
Rev. A | Page 13 of 32
1
2
3
4
5
6
7
8
INDEP
A1
W1
B1
RESET
A2
VSS
GND
16
15
14
13
12
11
10
9
ADDR1
SDA
SCL
VLOGIC
VDD
W2
B2
AD5122A/
AD5142A
TOP VIEW
(Not to Scale)
ADDR0
Figure 5. 16-Lead TSSOP Pin Configuration
Table 8. 16-Lead TSSOP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location.
If INDEP is enabled, it cannot be disabled by the software.
2
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low.
If this pin is not used, tie RESET to VLOGIC.
3
GND
Ground Pin, Logic Ground Reference.
4
A1
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
5
W1
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
6
B1
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
7
VSS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
8
A2
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
9
W2
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
10
B2
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
11
VDD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
12
VLOGIC
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
13
SCL
Serial Clock Line.
14
SDA
Serial Data Input/Output.
15
ADDR1
Programmable Address (ADDR1) for Multiple Package Decoding.
16
ADDR0
Programmable Address (ADDR0) for Multiple Package Decoding.


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