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AD1877 Datasheet(PDF) 16 Page - Analog Devices

Part No. AD1877
Description  Single-Supply 16-Bit Stereo ADC
Download  18 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD1877 Datasheet(HTML) 16 Page - Analog Devices

 
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AD1877
REV. A
–16–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
31
32
1
2
3
4
16
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
19
20
21
32
1
2
INPUT
HI
HI
517
18
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
LEFT TAG
LSB
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4
MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
L
RCK
INPUT
MSB
MSB
MSB
MSB
MSB
Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,
32-Bit Frame Mode, S/
M = Hl, RLJUST = LO, MSBDLY = Hl
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
1
2
3
4
5
17
SOUT
OUTPUT
TAG
OUTPUT
20
21
22
1
2
3
INPUT
WCLK
OUTPUT
HI
HI
618
19
MSB
LEFT TAG
MSB
LSB
RIGHT TAG
MSB-14
LSB
PREVIOUS DATA
MSB-1 MSB-2 MSB-3
LEFT DATA
MSB-4
MSB-3 MSB-4
LSB
MSB-1 MSB-2
RIGHT DATA
LSB
MSB-1
LEFT DATA
MSB
LEFT TAG
MSB
RIGHT TAG
L
RCK
INPUT
MSB
LSB
MSB
MSB
LSB
Figure 16. Serial Data Output Timing: Slave Mode, I 2S-Justified, 32-Bit Frame Mode,
S/
M = Hl, RLJUST= LO, MSBDLY = LO
BCLK OUTPUT (64 x FS)
RDEDGE = LO
CLKIN
INPUT
BCLK OUTPUT (64 x FS)
RDEDGE = HI
WCLK
OUTPUT
DATA & TAG
OUTPUTS
XMIT
XMIT
XMIT
XMIT
tDLYCKB
tBPWL
tBPWH
tBPWL
tBPWH
tDLYBLR
tDLYDT
tDLYBWR
tDLYBWF
L
RCK
OUTPUT
Figure 17. Master Mode Clock Timing


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