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AD14060BF-4 Datasheet(PDF) 31 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 31 Page - Analog Devices

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AD14060/AD14060L
–31–
REV. A
Link Ports: 2
× CLK Speed Operation
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Receive
Timing Requirements:
tSLDCL
Data Setup Before LCLK Low
2.5
2.25
ns
tHLDCL
Data Hold After LCLK Low
2.25
2.25
ns
tLCLKIW
LCLK Period (2
× Operation)
tCK/2
tCK/2
ns
tLCLKRWL
LCLK Width Low
4.5
5
ns
tLCLKRWH
LCLK Width High
4.25
4
ns
Switching Characteristics:
tDLAHC
LACK High Delay After CLKIN High
18 + DT/2
29.5 + DT/2
18 + DT/2
30.5 + DT/2
ns
tDLALC
LACK Low Delay After LCLK High
1
6
16.5
6
18.5
ns
Transmit
Timing Requirements:
tSLACH
LACK Setup Before LCLK High
19
19
ns
tHLACH
LACK Hold After LCLK High
–6.75
–6.5
ns
Switching Characteristics:
tDLCLK
LCLK Delay After CLKIN
9
9
ns
tDLDCH
Data Delay After LCLK High
3
2.75
ns
tHLDCH
Data Hold After LCLK High
–2
–2
ns
tLCLKTWL
LCLK Width Low
(tCK/4) – 1
(tCK/4) + 1
(tCK/4) – 0.75
(tCK/4) + 1.5
ns
tLCLKTWH
LCLK Width High
(tCK/4) – 1
(tCK/4) + 1
(tCK/4) – 1.5
(tCK/4) + 1
ns
tDLACLK
LCLK Low Delay After LACK High
(tCK/4) + 9
(3
× t
CL/4) + 17
(tCK/4) + 9
(3
× t
CL/4) + 17
ns
NOTE
1LACK will go low with t
DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.


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