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AD14060BF-4 Datasheet(PDF) 30 Page - Analog Devices |
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AD14060BF-4 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 44 page 
AD14060/AD14060L –30– REV. A Link Ports: 1 × CLK Speed Operation 5 V 3.3 V Parameter Min Max Min Max Units Receive Timing Requirements: tSLDCL Data Setup Before LCLK Low 3.5 3 ns tHLDCL Data Hold After LCLK Low 3 3 ns tLCLKIW LCLK Period (1 × Operation) tCK tCK ns tLCLKRWL LCLK Width Low 6 6 ns tLCLKRWH LCLK Width High 5 5 ns Switching Characteristics: tDLAHC LACK High Delay After CLKIN High 18 + DT/2 29.5 + DT/2 18 + DT/2 29.5 + DT/2 ns tDLALC LACK Low Delay After LCLK High 1 –3 13.5 –3 13.5 ns tENDLK LACK Enable from CLKIN 5 + DT/2 5 + DT/2 ns tTDLK LACK Disable from CLKIN 21 + DT/2 21 + DT/2 ns Transmit Timing Requirements: tSLACH LACK Setup Before LCLK High 18 20 ns tHLACH LACK Hold After LCLK High –7 –7 ns Switching Characteristics: tDLCLK LCLK Delay After CLKIN (1 × Operation) 16.5 17.5 ns tDLDCH Data Delay After LCLK High 3.5 3 ns tHLDCH Data Hold After LCLK High –3 –3 ns tLCLKTWL LCLK Width Low (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1 (tCK/2) + 1.25 ns tLCLKTWH LCLK Width High (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1.25 (tCK/2) + 1 ns tDLACLK LCLK Low Delay After LACK High (tCK/2) + 8.5 (3 × t CK/2) + 17.5 (tCK/2) + 8 (3 × t CK/2) + 18 ns tENDLK LDAT, LCLK Enable After CLKIN 5 + DT/2 5 + DT/2 ns tTDLK LDAT, LCLK Disable After CLKIN 21 + DT/2 21 + DT/2 ns Link Port Service Request Interrupts: 1 × and 2 × Speed Operations Timing Requirements: tSLCK LACK/LCLK Setup Before CLKIN Low 2 10 10 ns tHLCK LACK/LCLK Hold After CLKIN Low 2 2.5 2.5 ns NOTES 1LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill. 2Only required for interrupt recognition in the current cycle. |
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