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AD14060BF-4 Datasheet(PDF) 27 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 27 Page - Analog Devices

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AD14060/AD14060L
–27–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSTSCK
SBTS Setup Before CLKIN
12 + DT/2
12 + DT/2
ns
tHTSCK
SBTS Hold Before CLKIN
5.5 + DT/2
5.5 + DT/2
ns
Switching Characteristics:
tMIENA
Address/Select Enable After CLKIN
–1.5 – DT/8
–1.25 – DT/8
ns
tMIENS
Strobes Enable After CLKIN
1
–1.5 – DT/8
–1.5 – DT/8
ns
tMIENHG
HBG Enable After CLKIN
–1.5 – DT/8
–1.5 – DT/8
ns
tMITRA
Address/Select Disable After CLKIN
1 – DT/4
1 – DT/4
ns
tMITRS
Strobes Disable After CLKIN
1
2.5 – DT/4
2.5 – DT/4
ns
tMITRHG
HBG Disable After CLKIN
3 – DT/4
3 – DT/4
ns
tDATEN
Data Enable After CLKIN
2
9 + 5DT/16
9 + 5DT/16
ns
tDATTR
Data Disable After CLKIN
2
0 – DT/8
8 – DT/8
0 – DT/8
8 – DT/8
ns
tACKEN
ACK Enable After CLKIN
2
7.5 + DT/4
7.5 + DT/4
ns
tACKTR
ACK Disable After CLKIN
2
–1 – DT/8
7 – DT/8
–1 – DT/8
7 – DT/8
ns
tADCEN
ADRCLK Enable After CLKIN
–2 – DT/8
–2 – DT/8
ns
tADCTR
ADRCLK Disable After CLKIN
9 – DT/4
9 – DT/4
ns
tMTRHBG
Memory Interface Disable Before
HBG Low3
–1 + DT/8
–1 + DT/8
ns
tMENHBG
Memory Interface Enable After
HBG High3
18.5 + DT
18.5 + DT
ns
NOTES
1Strobes =
RD, WR, SW, PAGE, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address,
RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the
SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the
SBTS pin.
CLKIN
SBTS
ACK
MEMORY
INTERFACE
tMENHBG
tMTRHBG
HBG
MEMORY INTERFACE = ADDRESS,
RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
tMITRA, tMITRS, tMITRHG
tSTSCK
tHTSCK
tDATTR
tDATEN
tACKTR
tACKEN
tADCTR
tADCEN
ADRCLK
DATA
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
Figure 20. Three-State Timing


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