 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD14060BF-4 Datasheet(PDF) 25 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD14060BF-4 Datasheet(HTML) 25 Page - Analog Devices |
|
|
25 / 44 page 
AD14060/AD14060L –25– REV. A 5 V 3.3 V Parameter Min Max Min Max Units Read Cycle Timing Requirements: tSADRDL Address Setup/ CS Low Before RD Low1 0.5 0.5 ns tHADRDH Address Hold/ CS Hold Low After RD 0.5 0.5 ns tWRWH RD/WR High Width 6 6 ns tDRDHRDY RD High Delay After REDY (O/D) Disable 0.5 0.5 ns tDRDHRDY RD High Delay After REDY (A/D) Disable 0.5 0.5 ns Switching Characteristics: tSDATRDY Data Valid Before REDY Disable from Low 1.5 1.5 ns tDRDYRDL REDY (O/D) or (A/D) Low Delay After RD Low 11 11.5 ns tRDYPRD REDY (O/D) or (A/D) Low Pulsewidth for Read 45 + DT 45 + DT ns tHDARWH Data Disable After RD High 1.5 9 1.5 9.5 ns Write Cycle Timing Requirements: tSCSWRL CS Low Setup Before WR Low 0.5 0.5 ns tHCSWRH CS Low Hold After WR High 0.5 0.5 ns tSADWRH Address Setup Before WR High 5.5 5.5 ns tHADWRH Address Hold After WR High 2.5 2.5 ns tWWRL WR Low Width 7 7 ns tWRWH RD/WR High Width 6 6 ns tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable 0.5 0.5 ns tSDATWH Data Setup Before WR High 5.5 5.5 ns tHDATWH Data Hold After WR High 1.5 1.5 ns Switching Characteristics: tDRDYWRL REDY (O/D) or (A/D) Low Delay After WR/CS Low 11 11.5 ns tRDYPWR REDY (O/D) or (A/D) Low Pulsewidth for Write 15 15 ns tSRDYCK REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 9 + 7DT/16 0 + 7DT/16 8 + 7DT/16 ns NOTE 1Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31–0 must be a non-MMS value 1/2 t CLK before RD or WR goes low or by t HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User’s Manual. CLKIN REDY (O/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE tSRDYCK REDY (A/D) Figure 19a. Synchronous REDY Timing Asynchronous Read/Write—Host to AD14060/AD14060L Use these specifications for asynchronous host processor accesses of an AD14060/AD14060L, after the host has asserted CS and HBR (low). After HBG is returned by the AD14060/ AD14060L, the host can drive the RD and WR pins to access the AD14060/AD14060L’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
