Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

AD14060BF-4 Datasheet(PDF) 22 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

AD14060BF-4 Datasheet(HTML) 22 Page - Analog Devices

Zoom Inzoom in Zoom Outzoom out
 22 / 44 page
background image
AD14060/AD14060L
–22–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSADRI
Address,
SW Setup Before CLKIN
15.5 + DT/2
15.5 + DT/2
ns
tHADRI
Address,
SW Hold Before CLKIN
4.5 + DT/2
4.5 + DT/2
ns
tSRWLI
RD/WR Low Setup Before CLKIN1
9.5 + 5DT/16
9.5 + 5DT/16
ns
tHRWLI
RD/WR Low Hold After CLKIN
–3.5 – 5DT/16
8 + 7DT/16
–3.5 – 5DT/16
8 + 7DT/16
ns
tRWHPI
RD/WR Pulse High
3
3
ns
tSDATWH
Data Setup Before
WR High
5.5
5.5
ns
tHDATWH
Data Hold After
WR High
1.5
1.5
ns
Switching Characteristics:
tSDDATO
Data Delay After CLKIN
20 + 5DT/16
20 + 5DT/16
ns
tDATTR
Data Disable After CLKIN
2
0 – DT/8
8 – DT/8
0 – DT/8
8 – DT/8
ns
tDACKAD
ACK Delay After Address,
SW3
10
10
ns
tACKTR
ACK Disable After CLKIN
3
–1 – DT/8
7 – DT/8
–1 – DT/8
7 – DT/8
ns
NOTES
1t
SRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
tSRWLI (min) = 4 + DT/8.
2See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3t
DACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.
Synchronous Read/Write —Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
The bus master must meet these (bus slave) timing requirements.
CLKIN
ADDRESS
SW
ACK
RD
DATA
(OUT)
WR
WRITE ACCESS
tSADRI
tHADRI
tDACKAD
tACKTR
tRWHPI
tHRWLI
tSRWLI
tSDDATO
tDATTR
tSRWLI
tHRWLI
tRWHPI
tHDATWH
tSDATWH
DATA
(IN)
READ ACCESS
Figure 17. Synchronous Read/Write—Bus Slave


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn