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AD14060BF-4 Datasheet(PDF) 18 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 18 Page - Analog Devices

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AD14060/AD14060L
–18–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tDAD
Address, Delay to Data Valid
1, 4
17.5 + DT + W
17.5 + DT + W
ns
tDRLD
RD Low to Data Valid1
11.5 + 5DT/8 + W
11.5 + 5DT/8 + W
ns
tHDA
Data Hold from Address
2
11
ns
tHDRH
Data Hold from
RD High2
2.5
2.5
ns
tDAAK
ACK Delay from Address
3, 4
13.5 + 7DT/8 + W
13.5 + 7DT/8 + W
ns
tDSAK
ACK Delay from
RD Low3
7.5 + DT/2 + W
7.5 + DT/2 + W
ns
Switching Characteristics:
tDRHA
Address Hold After
RD High
–0.5 + H
–0.5 + H
ns
tDARL
Address to
RD Low4
1.5 + 3DT/8
1.5 + 3DT/8
ns
tRW
RD Pulsewidth
12.5 + 5DT/8 + W
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
8 + 3DT/8 + HI
ns
tSADADC
Address Setup Before ADRCLK High
4
–0.5 + DT/4
–0.5 + DT/4
ns
W = (number of wait states specified in WAIT register)
× t
CK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet t
DAD or tDRLD or synchronous spec tSSDATI.
2Data Hold: User must meet t
HDA or tHDRH or synchronous spec tHDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3ACK Delay/Setup: User must meet t
DSAK or tDAAK or synchronous specification tSACKC.
4For
MSx, SW, BMS, the falling edge is referenced.
WR, DMAG
ACK
DATA
RD
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDAD
tSADADC
tDAAK
tHDRH
tHDA
tRWR
tDRLD
ADRCLK
(OUT)
tDRHA
tDSAK
Figure 14. Memory Read—Bus Master
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write – Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).


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