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AD14060BF-4 Datasheet(PDF) 16 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 16 Page - Analog Devices

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AD14060/AD14060L
–16–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Parameter
Min
Max
Min
Max
Units
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
100
25
100
ns
tCKL
CLKIN Width Low
7
8.75
ns
tCKH
CLKIN Width High
5
5
ns
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
3
3
ns
CLKIN
tCKH
tCK
tCKL
Figure 9. Clock Input
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Reset
Timing Requirements:
tWRST
RESET Pulsewidth Low1
4tCK
4tCK
ns
tSRST
RESET Setup Before CLKIN High2
14 + DT/2
tCK
14 + DT/2
tCK
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while
RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
RESET
tWRST
tSRST
Figure 10. Reset
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup Before CLKIN High1
18 + 3DT/4
18 + 3DT/4
ns
tHIR
IRQ2-0 Hold Before CLKIN High1
11.5 + 3DT/4
11.5 + 3DT/4
ns
tIPW
IRQ2-0 Pulsewidth2
2 + tCK
2 + tCK
ns
NOTES
1Only required for
IRQx recognition in the following cycle.
2Applies only if t
SIR and tHIR requirements are not met.
CLKIN
IRQ2-0
tIPW
tSIR
tHIR
Figure 11. Interrupts


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