AD14060/AD14060L

–16–

REV. A

40 MHz–5 V

40 MHz–3.3 V

Parameter

Min

Max

Min

Max

Units

Clock Input

Timing Requirements:

CLKIN Period

25

100

25

100

ns

CLKIN Width Low

7

8.75

ns

CLKIN Width High

5

5

ns

CLKIN Rise/Fall (0.4 V–2.0 V)

3

3

ns

CLKIN

Figure 9. Clock Input

5 V

3.3 V

Parameter

Min

Max

Min

Max

Units

Reset

Timing Requirements:

ns

14 + DT/2

14 + DT/2

ns

NOTES

RESET is

for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN

RESET

Figure 10. Reset

5 V

3.3 V

Parameter

Min

Max

Min

Max

Units

Interrupts

Timing Requirements:

18 + 3DT/4

18 + 3DT/4

ns

11.5 + 3DT/4

11.5 + 3DT/4

ns

ns

NOTES

IRQx recognition in the following cycle.

CLKIN

IRQ2-0

Figure 11. Interrupts