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AD14060BF-4 Datasheet(PDF) 10 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 10 Page - Analog Devices

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AD14060/AD14060L
–10–
REV. A
Pin
Type
Function
TCLKy1
I/O
Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK
pin has a 50 k
Ω internal pull-up resistor.
RCLKy1
I/O
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 k
Ω internal pull-up resistor.
TFSy1
I/O
Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
RFSy1
I/O
Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
FLAGy0
I/O/A
Flag Pins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
FLAG1
I/O/A
Flag Pins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-
21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals.
FLAGy2
I/O/A
Flag Pins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-
ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-
put, it can be used to signal external peripherals.
IRQy2-0
I/A
Interrupt Request Lines. (Individual
IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMAR1
I/A
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAR2
I/A
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG1
O/T
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG2
O/T
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
LyxCLK
I/O
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
1. Each LyxCLK pin has a 50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
LyxDAT3-0
I/O
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
1. Each LyxDAT pin has a
50 k
Ω internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
LyxACK
I/O
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)
1. Each LyxACK pin has a
50 k
Ω internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
EBOOTA
I
EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOTA is low, the LBOOTA and
BMSA inputs determine booting mode
for SHARC_A. See the following table. This signal is a system configuration selection which should
be hardwired.
LBOOTA
I
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is
low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired.
BMSA
I/O/T
2
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system,
BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired.
EBOOTBCD
I
EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired.
LBOOTBCD
I
LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selec-
tion which should be hardwired.


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