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AD14060BF-4 Datasheet(PDF) 9 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 9 Page - Analog Devices

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AD14060/AD14060L
–9–
REV. A
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State. (Common to all SHARCs) External devices can assert
SBTS (low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14060/AD14060L attempts to access external memory while
SBTS is asserted, the processor
will halt and the memory access will not be completed until
SBTS is deasserted. SBTS should only be
used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
HBR
I/A
Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L’s external bus. When
HBR is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert
HBG. To relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state.
HBR has priority
over all ADSP-2106x bus requests (
BR
6-1) in a multiprocessing system.
HBG
I/O
Host Bus Grant. (Common to all SHARCs) Acknowledges an
HBR bus request, indicating that the
host processor may take control of the external bus.
HBG is asserted (held low) by the AD14060/AD14060L
until
HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is
monitored by all others.
CSA
I/A
Chip Select. Asserted by host processor to select SHARC_A.
CSB
I/A
Chip Select. Asserted by host processor to select SHARC_B.
CSC
I/A
Chip Select. Asserted by host processor to select SHARC_C.
CSD
I/A
Chip Select. Asserted by host processor to select SHARC_D.
REDY (O/D)
O
Host Bus Acknowledge. (Common to all SHARCs) The AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP-
21060s to be active drive (A/D). REDY will only be output if the CS and
HBR inputs are asserted.
BR
6-1
I/O/S
Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own
BRx line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused
BRx pins should be pulled high; BR
4-1 must not be pulled high or low because they are outputs.
RPBA
I/S
Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.
CPAy (O/D)
I/O
Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has
an internal 5 k
Ω pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
DT0
O/T
Data Transmit (Common Serial Ports 0 to all SHARCs, TDM). DT pin has a 50 k
Ω internal pull-up
resistor.
DR0
I
Data Receive (Common Serial Ports 0 to all SHARCs, TDM). DR pin has a 50 k
Ω internal pull-up
resistor.
TCLK0
I/O
Transmit Clock (Common Serial Ports 0 to all SHARCs, TDM). TCLK pin has a 50 k
Ω internal
pull-up resistor.
RCLK0
I/O
Receive Clock (Common Serial Ports 0 to all SHARCs, TDM). RCLK pin has a 50 k
Ω internal pull-up
resistor.
TFS0
I/O
Transmit Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
RFS0
I/O
Receive Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
DTy1
O/T
Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 k
Ω internal pull-up resistor.
DRy1
I
Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 k
Ω internal pull-up resistor.


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