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AD14060BF-4 Datasheet(PDF) 36 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 36 Page - Analog Devices

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AD14060/AD14060L
–36–
REV. A
JTAG Test Access Port and Emulation
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tTCK
TCK Period
tCK
tCK
ns
tSTAP
TDI, TMS Setup Before TCK High
5
5
ns
tHTAP
TDI, TMS Hold After TCK High
6
6
ns
tSSYS
System Inputs Setup Before TCK Low
1
88ns
tHSYS
System Inputs Hold After TCK Low
1
18.5
19
ns
tTRSTW
TRST Pulsewidth
4tCK
4tCK
ns
Switching Characteristics:
tDTDO
TDO Delay from TCK Low
13
13
ns
tDSYS
System Outputs Delay After TCK Low
2
20
20
ns
NOTES
1System Inputs = DATA
47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, RPBA, IRQ2-0, FLAG2-0, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2System Outputs = DATA
47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR 6-1, CPA, FLAG2-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
TCK
tSTAP
tTCK
tHTAP
tDTDO
tSSYS
tHSYS
tDSYS
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
Figure 25. IEEE 11499.1 JTAG Test Access Port


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