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AD14060BF-4 Datasheet(PDF) 35 Page - Analog Devices

Part No. AD14060BF-4
Description  Quad-SHARC DSP Multiprocessor Family
Download  44 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14060BF-4 Datasheet(HTML) 35 Page - Analog Devices

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AD14060/AD14060L
–35–
REV. A
DT
DT
tDDTTE
tDDTEN
tDDTTI
tDDTIN
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
TCLK / RCLK
TCLK (EXT)
tSDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRI
tSFSI
tHFSI
tDFSE
tHFSE
tSCLKIW
DATA RECEIVE– INTERNAL CLOCK
tSDRE
DATA RECEIVE– EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKW
tHFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
tDDTI
tHDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSI
tHFSI
tSCLKIW
tDFSI
tHFSI
DATA TRANSMIT– INTERNAL CLOCK
tDDTE
tHDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSE
tHFSE
tDFSE
tSCLKW
tHFSE
DATA TRANSMIT– EXTERNAL CLOCK
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
tDCLK
LOW TO HIGH ONLY
TCLK (INT)
RCLK (INT)
TCLK, RCLK
TFS, RFS, DT
CLKIN
TFS (EXT)
tHTFSCK
tSTFSCK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 24. Serial Ports


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