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AD14160 Datasheet(PDF) 1 Page - Analog Devices

Part No. AD14160
Description  Quad-SHARC DSP Multiprocessor Family
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD14160 Datasheet(HTML) 1 Page - Analog Devices

 
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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD14160/AD14160L
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
Quad-SHARC®
DSP Multiprocessor Family
FUNCTIONAL BLOCK DIAGRAM
PERFORMANCE FEATURES
ADSP-21060 Core Processor (
.. .
4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two
from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
452-Lead Ceramic Ball Grid Array (CBGA)
1.85" (47 mm) Body Size
0.200" Max Height
0.050" Ball Pitch
29 Grams (typical)
JC = 0.36 C/W
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi-
processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance—density and lowest
cost— performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.
The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
ID2-0
CPA
SPORT 1
SPORT 0
TDI
ID2-0
CPA
SPORT 1
SPORT 0
TDO
ID2-0
CPA
SPORT 1
SPORT 0
LINK 0
LINK 5
TDO
LINK 0
LINK 5
TDI
SHARC_D
SHARC_A
SHARC_C
AD14160/
AD14160L
ID2-0
CPA
SPORT 1
SPORT 0
SHARC_B
LINK 0
LINK 5
TDI
LINK 0
LINK 5
TDO
SHARC BUS (ADDR
31-0, DATA47-0
, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR
6-1, RPBA, DMAR1.2, DMAG1.2)
s
s
s
s


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