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74LVC1G3157GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC1G3157GM Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 26 page 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 6 December 2012 3 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. Fig 3. Pin configuration SOT363 and SOT457 Fig 4. Pin configuration SOT886 Fig 5. Pin configuration SOT891, SOT1115 and SOT1202 74LVC1G3157 Y1 S GND Y0 Z 001aac356 1 2 3 6 VCC 5 4 74LVC1G3157 Z VCC S Y0 GND Y1 001aac357 34 25 16 Transparent top view 74LVC1G3157 GND 001aaf546 Y1 Y0 VCC S Z Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description Y1 1 independent input or output GND 2 ground (0 V) Y0 3 independent input or output Z 4 common output or input VCC 5 supply voltage S 6 select input Table 4. Function table[1] Input S Channel on LY0 HY1 |
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