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ADS6632A4A-5 Datasheet(PDF) 2 Page - A-Data Technology |
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ADS6632A4A-5 Datasheet(HTML) 2 Page - A-Data Technology |
2 / 8 page A-Data ADS6632A4A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and DQM0 ~ DQM3 A0~A11 Address Row / Column address are multiplexed on the same pins. Row address : RA0~RA10 Column address : CA0~CA7 BA0~BA1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ31 Data Data inputs / outputs are multiplexed on the same pins. DQM0~3 Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Address /CS /RAS /CAS /WE DQM Mode Register Address Buffer & Refresh Counter Column Address Buffer & Refresh Counter Bank0 Bank2 Bank3 Bank1 Amplifier Column Decoder Data Control Circuit DQ Rev 1.0 April, 2001 2 |
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