Electronic Components Datasheet Search
Z16F2810FI20EG Datasheet(PDF) 2 Page - Zilog, Inc.
ZILOG [Zilog, Inc.]
Z16F2810FI20EG Datasheet(HTML) 2 Page - Zilog, Inc.
/ 8 page
Z16F sEriEs Flash miCrOCONTrOllEr
high-pErFOrmaNCE 16-BiT Flash sOluTiON
16-BiT EmBEddEd Flash sOluTiONs
ZNEO Z16F Flash Controller Detailed Feature Set
ZNEO cpu cOrE
Zilog’s ZNEO Z16F CPU meets the continuing demand for faster and more code-efficient microcontrollers.
The ZNEO Z16F CPU features are as follows:
• Pipelined architecture: Fetch, Decode, and Execute
• 16 MB of Program memory address space for object code and data with 8- or 16-bit data paths
• 8-, 16-, and 32-bit ALU operations
• 24-bit stack with overflow protection
• Direct register-to-register architecture allows each memory address to function as an
accumulator. This improves execution time and decreases the required program memory
• New instructions improve execution efficiency for code developed using higher-level
programming languages including ‘C’
For more information on the core architecture, please refer to the ZNEO Z16F CPU User Manual (UM0188)
available for download at www.zilog.com.
chip flash memory
The products in the ZNEO Z16F Series feature up to 128 KB of non-volatile Flash memory with read/write/
erase capability. The Flash memory is programmed and erased in-circuit by either user code or through the
On-Chip Debugger (OCD). The Flash memory array is arranged in 2 KB pages. The 2 KB page is the mini-
mum Flash block size that is erased. The Flash memory is also divided into eight sectors, which is protected
from programming and erase operations on a per sector basis.
The ZNEO Z16F Series devices include a 12-channel ADC. The ADC converts an analog input signal to a
10-bit binary number. The features of the successive approximation ADC include:
• 12 analog input sources multiplexed with GPIO ports.
• 2.5 μs conversion time
• Automatic Time-Tag of results
• Programmable timing controls
The ZNEO Z16F devices feature a general-purpose comparator and an operational amplifier.
• Moderate speed comparator (200 ns propagation delay) with a maximum input offset of 5 mV
• Two-input, one-output operational amplifier with a typical open loop gain of 10,000 (80 dB)
The ZNEO Z16F devices feature a rich array of communication peripherals, including:
• 2 UARTs
- LIN Master/Slave
- IrDA Encoder/Decoder
- Multiprocessor 9-bit Mode
• Enhanced SPI (ESPI)
key hardware features
zneo cpu core
chip flash memory
Does ALLDATASHEET help your business so far?
[ DONATE ]
All Rights Reserved©
| English :
| Chinese :
| German :
| Japanese :
| Korean :
| Spanish :
| French :
| Italian :
| Polish :
| Vietnamese :