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IS43DR32801B Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc |
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IS43DR32801B Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc |
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3 / 44 page  Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. 00B 06/07/2012 IS43/46DR32801B Symbol Type Function CK,CK Input Clock:CKandCKaredifferentialclockinputs.Alladdressandcontrolinputsignals aresampledonthecrossingofthepositiveedgeofCKandnegativeedgeofCK. Output(read)dataisreferencedtothecrossingsofCKandCK(bothdirectionsof crossing). CKE Input ClockEnable:CKEHIGHactivates,andCKELOWdeactivates,internalclocksignals anddeviceinputbuffersandoutputdrivers.TakingCKELOWprovidesPrecharge Power-DownandSelfRefreshoperation(allbanksidle),orActivePower-Down(row Activeinanybank).CKEissynchronousforpowerdownentryandexit,andforself refreshentry.CKEisasynchronousforselfrefreshexit.AfterVREFhasbecome stableduringthepoweronandinitializationsequence,itmustbemaintainedfor properoperationoftheCKEreceiver.Forproperself-refreshentryandexit,VREF mustbemaintainedtothisinput.CKEmustbemaintainedHIGHthroughoutreadand writeaccesses.Inputbuffers,excludingCK,CK,ODTandCKEaredisabledduring power-down.Inputbuffers,excludingCKE,aredisabledduringselfrefresh. CS Input ChipSelect:AllcommandsaremaskedwhenCSisregisteredHIGH.CSprovidesfor externalRankselectiononsystemswithmultipleRanks.CSisconsideredpartofthe commandcode. ODT Input OnDieTermination:ODT(registeredHIGH)enablesterminationresistanceinternal totheDDR2SDRAM.Whenenabled,ODTisappliedtoeachDQ,DQS,DQS,DQM signals.TheODTpinwillbeignorediftheEMR(1)isprogrammedtodisableODT. RAS,CAS,WE Input CommandInputs:RAS,CASandWE(alongwithCS)definethecommandbeing entered. (DM0-DM3) Input InputDataMask:DMisaninputmasksignalforwritedata.Inputdataismasked whenDMissampledHIGHcoincidentwiththatinputdataduringaWriteaccess.DM issampledonbothedgesofDQS.AlthoughDMpinsareinputonly,theDMloading matchestheDQandDQSloading.ThefunctionofDMisenabledbyEMRScommand toEMR(1). BA0-BA1 Input BankAddressInputs:BA0-BA1definetowhichbankanActive,Read,Writeor Prechargecommandisbeingapplied.Bankaddressalsodeterminesifthemode registeroroneoftheextendedmoderegistersistobeaccessedduringaMRSor EMRScommandcycle. A0-A12 Input AddressInputs:ProvidetherowaddressforActivecommandsandthecolumn addressandAutoPrechargebitforRead/Writecommandstoselectonelocation outofthememoryarrayintherespectivebank.A10issampledduringaPrecharge commandtodeterminewhetherthePrechargeappliestoonebank(A10LOW)orall banks(A10HIGH).Ifonlyonebankistobeprecharged,thebankisselectedbyBA0- BA1.Theaddressinputsalsoprovidetheop-codeduringMRSorEMRScommands. PIN DESCRIPTION TABLE |
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