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W88113C Datasheet(PDF) 28 Page - Winbond |
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W88113C Datasheet(HTML) 28 Page - Winbond |
28 / 47 page W88113C Publication Release Date: Mar. 1999 - 24 - Revision 0.61 Bit 1: DRST - Decoder Reset Setting this bit to high resets decoding logic, including: • SRIEN (01h.w5) ← 0 • CTRL0 (0Ah,w) ← 00h • CTRL1 (0Bh,w) ← 00h • CTRLW (10h,w) ← 00h • STAT0-2 (0Ch-0Eh,r) ← 00h • STAT3 (0Fh,r) ← 80h • TARSTA (80h,r) ← 00h DRST is automatically cleared by itself. CRTRG - Correction Retry Trigger - (write 11h) Writing register CRTRG, regardless of what data is written, triggers the decoding logic to perform another correction sequence to the same block. Bit 7-1: Reserved Bit 0: CRRL - Correction Retry Register Load Setting this bit high while writing register CRTRG (11h,w) re-loads the setting of EDCEN (0Ah.w5), QCEN (0Ah.w1), or PCEN (0Ah.w0) to decoding logic. Decoder Parameter Updated at the end of sync Updated by writing CRRL EDCEN (0Ah.w5) yes yes QCEN (0Ah.w1) yes yes PCEN (0Ah.w0) yes yes ACEN (0Ah.w4) yes no BUFEN (0Ah.w2) yes no M2RQ (0Bh.w3) yes no F2RQ (0Bh.w2) yes no MCRQ (0Bh.w1) yes no |
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