LC75808W

No.6370-32/38

Sample Application Circuit 3

1/9 duty, 1/4 bias drive technique (for use with normal panels)

Note: *6. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise

time when power is applied and the logic block power supply voltage VDD fall time when power drops are

both at least 1ms, as the LC75808W is reset by the VDET.

*7. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to

ground.

*8. If the function of the INH pin is not used, the INH pin must be connected to the logic block power supply

VDD.

*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1k

Ω to

10k

Ω) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

OPEN

COM10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S56

S57

S58

S59

S60

P1

P2

P3

P4

OPEN

C

C

C

*6

OSC

INH * 8

*9

CE

CL

DI

DO

K

I

5

K

I

4

K

I

3

K

I

2

K

I

1

K

S

6

K

S

5

K

S

4

K

S

3

K

S

2

K

S

1

LCD panel

Key matrix

(up to 30 keys)

A12924

+5V

+8V

C

From the controller

To the controller

To the controller

power supply

Used with the backlight

controller or other circuit.

general-purpose output ports

VDD

TEST

VSS

VLCD

VLCD0

VLCD1

VLCD2

VLCD3

VLCD4*7