Truth Table

The truth table for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow. [2, 3, 4, 5, 6, 7]

Operation

K

RPS WPS

DQ

DQ

DQ

DQ

Write cycle:

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

L–H

H[8]

 D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)

Read cycle:

Load address on the rising

edge of K; wait one and a

half cycle; read data on two

consecutive C and C rising

edges.

L–H

X

Q(A) at C(t + 1)

 Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)

NOP: No operation

L–H

H

H

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

Standby: Clock stopped

Stopped

X

X

Previous state

Previous state

Previous state

Previous state

Write Cycle Descriptions

The write cycle description table for CY7C1311KV18 and CY7C1313KV18 are as follows. [2, 10]

K

K

Comments

L

L

L–H

–

During the data portion of a write sequence



CY7C1311KV18

CY7C1313KV18

L

L

–

L–H During the data portion of a write sequence:

CY7C1311KV18

CY7C1313KV18

L

H

L–H

–

During the data portion of a write sequence:

CY7C1311KV18

CY7C1313KV18

L

H

–

L–H During the data portion of a write sequence



CY7C1311KV18

CY7C1313KV18

H

L

L–H

–

During the data portion of a write sequence



CY7C1311KV18

CY7C1313KV18

H

L

–

L–H During the data portion of a write sequence



CY7C1311KV18

CY7C1313KV18

H

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

2. X = ‘Don't Care’, H = Logic HIGH, L = Logic LOW,

3. Device powers up deselected with the outputs in a tristate condition.

4. ‘A’ represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

5. ‘t’ represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ‘t’ clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a ‘Don’t Care’ for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.

different portions of a write cycle, as long as the setup and hold requirements are achieved.

CY7C1311KV18, CY7C1911KV18

CY7C1313KV18, CY7C1315KV18

Document Number: 001-58904 Rev. *E

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