W83194R-630A datasheet(4/11 Pages) WINBOND

Part #	W83194R-630A

Description	166MHZ CLOCK FOR SIS CHIPSET

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Manufacturer	WINBOND [Winbond]

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W83194R-630A

PRELIMINARY

Publication Release Date: Nov. 1999

- 4 -

Revision 0.65

PCI free-running clock during normal operation.

PCICLK 1/ *FS2

8

I/O

Latched input for FS2 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

PCI clock during normal operation.

PCICLK 2/ *MODE

9

I/O

Latched input for MODE at initial power up for input

selection of CPU_STOP#, PCI_STOP# and PD#.

When MODE=1, the above pins are SDRAM clock

outputs. When MODE=0, the pins are inputs ACPI

pins.

PCI clock during normal operation.

PCICLK [ 3:6 ]

11,12,13,14

OUT

Low skew (< 250ps) PCI clock outputs.

5.3 I

2C Control Interface

SYMBOL

I/O

FUNCTION

*SDATA

23

I/O

Serial data of I

2C 2-wire control interface

*SDCLK

24

IN

Serial clock of I

2C 2-wire control interface

5.4 Fixed Frequency Outputs

SYMBOL

I/O

FUNCTION

REF0X2 / *FS3

2

I/O

3.3V, 14.318MHz reference clock output .

Internal 250k

Ω pull-up.

Latched input for FS3 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

REF1

48

I/O

3.3V , 14.318MHz reference clock output.

24_48MHz/

SEL2.5_3.3#

25

I/O

SEL2.5_3.3# controls the Vdd of CPU. If logic 0 at

power on, VddLCPU=3.3V. If logic 1, VddLCPU=2.5

24MHz or 48MHz selected by I2C for Super I/O.

48MHz / *FS0

26

I/O

Internal 250k

Ω pull-up.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks. 48MHz output for USB during normal

operation.

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