CY7C1311KV18, CY7C1911KV18

CY7C1313KV18, CY7C1315KV18

Document Number: 001-58904 Rev. *E

Page 7 of 32

Pin Definitions

Pin Name

I/O

Pin Description

Input-

synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

CY7C1311KV18

CY7C1911KV18

CY7C1313KV18

CY7C1315KV18

WPS

Input-

synchronous

Write Port Select

 Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

Input-

synchronous

Nibble Write Select 0, 1

 Active LOW (CY7C1311KV18 only). Sampled on the rising edge of the K

and K clocks when write operations are active. Used to select which nibble is written into the device

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

Input-

synchronous

Byte Write Select 0, 1, 2, and 3

 Active LOW. Sampled on the rising edge of the K and K clocks when

write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C1911KV18

CY7C1313KV18

CY7C1315KV18

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2 M × 8 (4 arrays each of 512 K × 8) for CY7C1311KV18, 2 M × 9 (4 arrays each of

512 K × 9) for CY7C1911KV18, 1 M × 18 (4 arrays each of 256 K × 18) for CY7C1313KV18 and

512 K × 36 (4 arrays each of 128 K × 36) for CY7C1315KV18. Therefore, only 19 address inputs are

needed to access the entire memory array of CY7C1311KV18 and CY7C1911KV18, 18 address inputs

for CY7C1313KV18 and 17 address inputs for CY7C1315KV18. These inputs are ignored when the

appropriate port is deselected.

Outputs-

synchronous

Data Output Signals. These pins drive out the requested data when the read operation is active. Valid

data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in

CY7C1311KV18

CY7C1911KV18

CY7C1313KV18

CY7C1315KV18

RPS

Input-

synchronous

Read Port Select

 Active LOW. Sampled on the rising edge of positive input clock (K). When active,

a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access

is allowed to complete and the output drivers are automatically tristated following the next rising edge of

the C clock. Each read access consists of a burst of four sequential transfers.

C

Input clock

Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board

back to the controller. See Application Example on page 10 for further details.

C

Input clock

Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board

back to the controller. See Application Example on page 10 for further details.

K

Input clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

edge of K.

K

Input clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device