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CY2DL15110AZIT Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY2DL15110AZIT Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 13 page CY2DL15110 Document Number: 001-69398 Rev. *C Page 3 of 13 Pinouts Figure 1. Pin Diagram - CY2DL15110 1 234 567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q2# Q2 Q1# Q1 Q0# Q0 VDD VDD Q7 Q7# Q8 Q8# Q9 Q9# VSS CY2DL15110 VSS Pin Definitions Pin No. Pin Name Pin Type Description 1 NC No connection 2 IN_SEL Input Input clock select pin. Low-voltage complementary metal oxide semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL). When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active 3 IN0 Input LVDS input clock. Active when IN_SEL = Low 4 IN0# Input LVDS complementary input clock. Active when IN_SEL = Low 5VBB Output LVDS reference voltage output 6 IN1 Input LVDS input clock. Active when IN_SEL = High 7 IN1# Input LVDS complementary input clock. Active when IN_SEL = High 8 OE Input Output enable. LVCMOS/LVTTL; When OE = Low, Q(0:9) and Q(0:9)# outputs are disabled 9, 25 VSS Power Ground 10, 12, 14, 17, 19, 21, 23, 26, 28, 30 Q(0:9)# Output LVDS complementary output clocks 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 Q(0:9) Output LVDS output clocks 16, 32 VDD Power Power supply |
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